Abstract: A shadow softening GPU and method. One embodiment of the GPU is configured to render a shadow cast by a surface occluding a light source and includes: (1) a fetching circuit operable to retrieve a depth value from a texture associated with the surface and a depth comparison result in a single fetch operation, and (2) a shadow softening circuit configured to respectively employ the depth comparison result and the depth value to identify the surface as a blocker and attenuate the light source for a pixel.

Abstract: A tile shader for screen space of a graphics pipeline, a method of rendering graphics and a graphics processing unit are disclosed. In one embodiment, the tile shader includes: (1) an input interface configured to receive a tile of pixels for processing and (2) a tile processor configured to perform tile-level processing of the pixels.

Abstract: A deferred shading GPU, geometry data structure and method. One embodiment of the geometry data structure is found in a graphics processing subsystem operable to render a scene having a pixel represented by samples. The graphics processing subsystem includes: (1) a memory configured to store a geometry data structure associated with the pixel containing surface fragment coverage masks associated with the samples, and (2) a GPU configured to employ the surface fragment coverage masks to carry out deferred shading on the pixel.

Abstract: A system and method for allocating shared memory of differing properties to shared data objects and a hybrid stack data structure. In one embodiment, the system includes: (1) a hybrid stack creator configured to create, in the shared memory, a hybrid stack data structure having a lower portion having a more favorable property and a higher portion having a less favorable property and (2) a data object allocator associated with the hybrid stack creator and configured to allocate storage for shared data object in the lower portion if the lower portion has a sufficient remaining capacity to contain the shared data object and alternatively allocate storage for the shared data object in the higher portion if the lower portion has an insufficient remaining capacity to contain the shared data object.

Abstract: A method, a receiver and computer program product for reporting at least one channel quality indicator from a receiver to a transmitter in a MIMO system are disclosed herein. In one embodiment, the receiver receives one or more data streams transmitted by the transmitter wherein the data streams are processed by the transmitter using a transmission precoding matrix W prior to transmission to the receiver. The receiver estimates a preferred precoding matrix Wp which is preferred by the receiver and processes the received data streams using the transmission precoding matrix W, such that the effective channel G at the output of the signal processing module is dependent upon the transmission precoding matrix W used by the transmitter. The receiver determines a second effective channel Gp, uses it to determine the at least one channel quality indicator and transmits the determined at least one channel quality indicator to the transmitter.

Abstract: An apparatus comprising a wireless modem for use at a terminal, the modem being adapted to connect to the terminal via a first connection, and to connect via a second, wireless connection to a gateway between a wireless cellular network and a further, packet-based network. The modem is operable to connect to the gateway via the second connection using a point-to-point link protocol that does not require a physical address for the gateway, and is operable to connect to the host terminal via the first connection using a point-to-multipoint link protocol that supports point-to-multipoint connection and does require a physical address for the gateway. The modem is configured to intercept a message being conveyed between the gateway and the terminal, to generate a substitute address that identifies an interface of the modem, and in response to intercepting the message to communicate the substitute address to the terminal.

Abstract: Embodiments for positioning rising and/or filling edges of data strobe signals are disclosed. One example embodiment may comprise receiving a data signal, positioning an edge of a first delayed data strobe signal associated with the data signal by a first programmable amount, and positioning an edge of a second delayed data strobe signal associated with the data signal by a second programmable amount, wherein the second delayed data strobe signal is shifted approximately one bit-time in relation to the first delayed data strobe signal.

Abstract: An interface device having a video BIOS component. The device includes a substrate for implementing a mother board connection and implementing a GPU (graphics processor unit) connection. A video BIOS component is mounted on the substrate for providing video BIOS functions for the computer system.

Abstract: A memory system is disclosed. The memory system comprises a circuit board and at least two memory devices mounted on the circuit board. Each of the at least two memory devices includes a plurality of pins for receiving and providing signals. At least a first portion of the pins of one of the at least two memory devices are coupled to at least a second portion of the pins of the other at least two memory devices such that a pair of the first portion coupled to a pin of the second portion forms a coupled load. The coupled load then appears as one load. Accordingly, in a system in accordance with the present invention, at least two memory devices are provided on a circuit board. Each of the at least two memory devices includes a plurality of pins.

Abstract: A method and apparatus for grouping texture data to increase storage throughput. Texels are addressed and stored according to adjacency to enable retrieval of a plurality of texels (a cache entry) with only a single address space request. Individual texel position is then derived using a simple adjacency formula. The preferred method and apparatus are compatible with both tiled data and linear data storage formats.

Abstract: A graphics pipeline system is provided for graphics processing. Such system includes a transform module adapted for being coupled to a vertex attribute buffer for receiving vertex data. The transform module serves to transform the vertex data from object space to screen space. Coupled to the transform module is a lighting module which is positioned on the single semiconductor platform for performing lighting operations on the vertex data received from the transform module. Also included is a rasterizer coupled to the lighting module and positioned on the single semiconductor platform for rendering the vertex data received from the lighting module.

Abstract: A circuit for accelerating processing of pixel data being provided to a frame buffer comprising circuitry for determining that pixel values vary linearly over a scan line of a polygon to be rendered, linear interpolation circuitry for providing pixel values using a process of linear interpolation between accurately determined pixel values, and a circuit for collecting pixel values to be written to a frame buffer until a significant number of pixel values may be written together.

Abstract: An input circuit for an input/output device adapted for use in a computer system including a first section having a storage circuit holding physical addresses of input/output devices which are translations of selected input/output bus addresses, and a comparator circuit for testing an address in a command from application programs including both data and an address for the data with the recently accessed addresses to obtain a translation from the storage circuit; and a second section including a hash table including translations of physical addresses to be placed in the storage circuit.