Patents Assigned to NVidia
-
Patent number: 11973501Abstract: A multi-rank circuit system includes multiple transmitters each switchably coupled to a first end of a shared input/output (IO) channel and a unified receiver coupled to a second end of the shared IO channel. The unified receiver is coupled to apply a preconfigured analog reference voltage to set a differential output of the unified receiver, and further configured to apply a variable digital code to adjust the differential output according to a particular one of the transmitters that is switched to the shared IO channel.Type: GrantFiled: April 27, 2022Date of Patent: April 30, 2024Assignee: NVIDIA CORP.Inventors: Jiwang Lee, Jaewon Lee, Hsuche Nee, Po-Chien Chiang, Wen-Hung Lo, Michael Ivan Halfen, Abhishek Dhir
-
Patent number: 11974416Abstract: Systems and methods for cooling a datacenter are disclosed. In at least one embodiment, one or more flow controllers is associated with a cold plate and with a thermosyphon condenser that is elevated with respect to a cold plate so that two-phase fluid is enabled for gravity-assisted downflow in a liquid phase to a cold plate for absorption of heat and is enabled for buoyancy-driven upflow through a riser tube into a thermosyphon condenser for dissipation of heat of at least one computing device.Type: GrantFiled: April 23, 2021Date of Patent: April 30, 2024Assignee: Nvidia CorporationInventor: Ali Heydari
-
Patent number: 11973060Abstract: A TSV of a first semiconductor die may extend from a semiconductor substrate of the first semiconductor die through at least one metallization layer of the die to connect to a metallization layer to supply power to the second semiconductor die. By extending the TSV, resistance may be reduced, allowing for enhanced power delivery to the second semiconductor die. Resistance may be further reduced by allowing for the TSV to connect to a thicker metallization layer than would otherwise be possible. Also, in some embodiments, the TSV may connect to a metallization layer that is suitable for supplying power to both semiconductor dies. The first semiconductor die may be a top die or a bottom die in a face-to-face arrangement. Disclosed concepts may be extended to any number of dies included in a die stack that includes the face-to-face arrangement.Type: GrantFiled: August 26, 2021Date of Patent: April 30, 2024Assignee: NVIDIA CorporationInventors: Joseph Greco, Joseph Minacapelli
-
Patent number: 11972281Abstract: A first intermediate representation of a first portion of a source code implementing an application and a second intermediate representation of a second portion of the source code is received by a processing device. The first intermediate representation and the second intermediate representation is merged, at run-time, into a merged intermediate representation, wherein the first intermediate representation includes a reference to a function in the second intermediate representation. An execution flow transfer instruction within the merged intermediate representation is identified based on a run-time value of a parameter of the application. The execution flow transfer instruction references the function. A set of executable instructions implementing the function is identified within the merged intermediate representation. The execution flow transfer instruction is replaced with a copy of the set of executable instructions implementing the function.Type: GrantFiled: March 7, 2022Date of Patent: April 30, 2024Assignee: NVIDIA CorporationInventors: Michael Murphy, Shelton George Dsouza, Shandeep Nagori, Thibaut Lutz
-
Patent number: 11971790Abstract: The disclosure describes a method of monitoring the dynamic power consumption of ReRAM crossbars and determines the occurrence of faults when a changepoint is detected in the monitored power-consumption time series. Statistical features are computed before and after the changepoint and train a predictive model using machine-learning techniques. In this way, the computationally expensive fault localization and error-recovery steps are carried out only when a high fault rate is estimated. With the proposed fault-detection method and the predictive model, the test time is significantly reduced while high classification accuracy for well-known AI/ML datasets using a ReRAM-based computing system (RCS) can still be ensured.Type: GrantFiled: August 24, 2021Date of Patent: April 30, 2024Assignee: NVIDIA CorporationInventors: Krishnendu Chakrabarty, Mengyun Liu
-
Patent number: 11972188Abstract: To ensure proper operation (e.g., speed and/or function) of standard cells fabricated within an integrated circuit a minimum potential difference between the high and low power supply rails needs to be maintained. IR drop refers to a reduction in the potential difference between the power supply rails and is caused when the switching activity of cells that share a power supply rail is greater than can be provided at a particular time. Before fabrication, placement of the cells is reorganized within bounding box regions. Power density across the power rails within each bounding box is normalized based on spatial and temporal power density characteristics of each cell. The reorganization is IR aware and has minimal impact on timing and IR drop is mitigated because distributing current consumption between the supply rails reduces current spikes and IR drops.Type: GrantFiled: October 19, 2021Date of Patent: April 30, 2024Assignee: NVIDIA CorporationInventors: Shaurakar Das, Haoxing Ren, Santosh Santosh, SeshasaiJyothi Kolli, Muhammad Arif Mirza, Sreedhar Pratty
-
Patent number: 11971774Abstract: A datacenter power management system and method is disclosed. A plurality of computing units are enabled to operate at a second frequency, higher than a first frequency, in response to determining from respective power coefficients for these computing units, that a power level at this higher frequency remains below a power budget.Type: GrantFiled: October 13, 2020Date of Patent: April 30, 2024Assignee: Nvidia CorporationInventors: Benjamin Faulkner, Mini Rawat, Sreedhar Narayanaswamy, Tom Li, Swanand Bindoo, Divya Ramakrishnan
-
Patent number: 11972354Abstract: Artificial neural networks (ANNs) are computing systems that imitate a human brain by learning to perform tasks by considering examples. By representing an artificial neural network utilizing individual paths each connecting an input of the ANN to an output of the ANN, a complexity of the ANN may be reduced, and the ANN may be trained and implemented in a much faster manner when compared to an implementation using fully connected ANN graphs.Type: GrantFiled: February 15, 2022Date of Patent: April 30, 2024Assignee: NVIDIA CORPORATIONInventors: Alexander Keller, Gonçalo Filipe Torcato Mordido, Noah Jonathan Gamboa, Matthijs Jules Van Keirsbilck
-
Publication number: 20240135618Abstract: In various examples, artificial intelligence (AI) agents can be generated to synthesize more natural motion by simulated actors in various visualizations (such as video games or simulations). AI agents may employ one or more machine learning models and techniques, such as reinforcement learning, to enable synthesis of motion with enhanced realism. The AI agent can be trained based on widely-available broadcast video data, without the need for more costly and limited motion capture data. To account for the lower quality of such video data, various techniques can be employed, such as taking into account the motion of joints, and applying physics-based constraints on the actors, resulting in higher quality, more lifelike motion.Type: ApplicationFiled: May 23, 2023Publication date: April 25, 2024Applicant: NVIDIA CorporationInventors: Haotian Zhang, Ye Yuan, Jason Peng, Viktor Makoviichuk, Sanja Fidler
-
Patent number: 11966228Abstract: In various examples, a current claimed set of points representative of a volume in an environment occupied by a vehicle at a time may be determined. A vehicle-occupied trajectory and at least one object-occupied trajectory may be generated at the time. An intersection between the vehicle-occupied trajectory and an object-occupied trajectory may be determined based at least in part on comparing the vehicle-occupied trajectory to the object-occupied trajectory. Based on the intersection, the vehicle may then execute the first safety procedure or an alternative procedure that, when implemented by the vehicle when the object implements the second safety procedure, is determined to have a lesser likelihood of incurring a collision between the vehicle and the object than the first safety procedure.Type: GrantFiled: December 16, 2022Date of Patent: April 23, 2024Assignee: NVIDIA CorporationInventors: David Nister, Hon-Leung Lee, Julia Ng, Yizhou Wang
-
Patent number: 11966480Abstract: Apparatuses, systems, and techniques for supporting fairness of multiple context sharing cryptographic hardware. An accelerator circuit includes a copy engine (CE) with AES-GCM hardware configured to perform both encryption and authentication of data transfers for multiple applications or multiple data streams in a single application or belonging to a single user. The CE splits a data transfer of a specified size into a set of partial transfers. The CE sequentially executes the set of partial transfers using a context for a period of time (e.g., a timeslice) for an application. The CE stores in a secure memory for the application one or more data for encryption or decryption (e.g., a hash key, a block counter, etc.) computed from a last partial transfer. The one or more data for encryption or decryption are retrieved and used when data transfers for the application is resumed by the CE.Type: GrantFiled: March 10, 2022Date of Patent: April 23, 2024Assignee: Nvidia CorporationInventors: Adam Hendrickson, Vaishali Kulkarni, Gobikrishna Dhanuskodi, Naveen Cherukuri, Wish Gandhi, Raymond Wong
-
Patent number: 11966765Abstract: Systems and methods are disclosed for throttling memory bandwidth accessed by virtual machines (VMs). A technique for dynamically throttling the virtual computer processing units (vCPUs) assigned to a VM (tenant) controls the memory access rate of the VM. When the memory is shared by multiple VMs in a cloud-computing environment, one VM increasing its memory access rate may cause another VM to suffer memory access starvation. This behavior violates the principle of VM isolation in cloud computing. In contrast to conventional systems, a software solution for dynamically throttling the vCPUs may be implemented within a hypervisor and is therefore portable across CPU families and doesn't require specialized server-class CPU capabilities or limit the system configuration.Type: GrantFiled: September 9, 2020Date of Patent: April 23, 2024Assignee: NVIDIA CorporationInventors: Santosh Kumar Ravindranath Shukla, Andrew Currid, Chenghuan Jia, Arpit R. Jain, Shounak Santosh Deshpande
-
Patent number: 11966673Abstract: In various examples, a sensor model may be learned to predict virtual sensor data for a given scene configuration. For example, a sensor model may include a deep neural network that supports generative learning—such as a generative adversarial network (GAN). The sensor model may accept an encoded representation of a scene configuration as an input using any number of data structures and/or channels (e.g., concatenated vectors, matrices, tensors, images, etc.), and may output virtual sensor data. Real-world data and/or virtual data may be collected and used to derive training data, which may be used to train the sensor model to predict virtual sensor data for a given scene configuration. As such, one or more sensor models may be used as virtual sensors in any of a variety of applications, such as in a simulated environment to test features and/or functionality of one or more autonomous or semi-autonomous driving software stacks.Type: GrantFiled: March 13, 2020Date of Patent: April 23, 2024Assignee: NVIDIA CorporationInventors: Steen Kristensen, Alessandro Ferrari, Ayman Elsaeid
-
Patent number: 11966348Abstract: Methods of operating a serial data bus divide series of data bits into sequences of one or more bits and encode the sequences as N-level symbols, which are then transmitted at multiple discrete voltage levels. These methods may be utilized to communicate over serial data lines to improve bandwidth and reduce crosstalk and other sources of noise.Type: GrantFiled: January 28, 2019Date of Patent: April 23, 2024Assignee: NVIDIA Corp.Inventors: Donghyuk Lee, James Michael O'Connor
-
Patent number: 11966737Abstract: Systems and methods for an efficient and robust multiprocessor-coprocessor interface that may be used between a streaming multiprocessor and an acceleration coprocessor in a GPU are provided. According to an example implementation, in order to perform an acceleration of a particular operation using the coprocessor, the multiprocessor: issues a series of write instructions to write input data for the operation into coprocessor-accessible storage locations, issues an operation instruction to cause the coprocessor to execute the particular operation; and then issues a series of read instructions to read result data of the operation from coprocessor-accessible storage locations to multiprocessor-accessible storage locations.Type: GrantFiled: September 2, 2021Date of Patent: April 23, 2024Assignee: NVIDIA CORPORATIONInventors: Ronald Charles Babich, Jr., John Burgess, Jack Choquette, Tero Karras, Samuli Laine, Ignacio Llamas, Gregory Muthler, William Parsons Newhall, Jr.
-
Patent number: 11966835Abstract: A sparse convolutional neural network accelerator system that dynamically and efficiently identifies fine-grained parallelism in sparse convolution operations. The system determines matching pairs of non-zero input activations and weights from the compacted input activation and weight arrays utilizing a scalable, dynamic parallelism discovery unit (PDU) that performs a parallel search on the input activation array and the weight array to identify reducible input activation and weight pairs.Type: GrantFiled: January 23, 2019Date of Patent: April 23, 2024Assignee: NVIDIA CORP.Inventors: Ching-En Lee, Yakun Shao, Angshuman Parashar, Joel Emer, Stephen W. Keckler
-
Patent number: 11968040Abstract: Various embodiments and implementations of graph-neural-network (GNN)-based decoding applications are disclosed. The GNN-based decoding schemes are broadly applicable to different coding schemes, and capable of operating on both binary and non-binary codewords, in different implementations. Advantageously, the inventive GNN-based decoding is scalable, even with arbitrary block lengths, and not subject to typical limits with respect to dimensionality. Decoding performance of the inventive GNN-based techniques demonstrably matches or outpaces BCH and LDPC (both regular and 5G NR) decoding algorithms, while exhibiting improvements with respect to number of iterations required and scalability of the GNN-based approach. These inventive concepts are implemented, according to various embodiments, as methods, systems, and computer program products.Type: GrantFiled: March 7, 2023Date of Patent: April 23, 2024Assignee: NVIDIA CORPORATIONInventors: Jakob Hoydis, Sebastian Cammerer, Faycal Ait Aoudia, Alexander Keller
-
Patent number: 11967396Abstract: A multi-rank system includes multiple circuit ranks communicating over a common data line to multiple data receivers, each corresponding to one or more of the ranks and each having a corresponding reference voltage generator and clock timing adjustment circuit, such that a rank to communicate on the shared data line is switched without reconfiguring outputs of either the reference voltage generators or the clock timing adjustment circuits.Type: GrantFiled: April 27, 2022Date of Patent: April 23, 2024Assignee: NVIDIA CORP.Inventors: Wen-Hung Lo, Michael Ivan Halfen, Abhishek Dhir, Jaewon Lee
-
Patent number: 11967024Abstract: A technique is described for extracting or constructing a three-dimensional (3D) model from multiple two-dimensional (2D) images. In an embodiment, a foreground segmentation mask or depth field may be provided as an additional supervision input with each 2D image. In an embodiment, the foreground segmentation mask or depth field is automatically generated for each 2D image. The constructed 3D model comprises a triangular mesh topology, materials, and environment lighting. The constructed 3D model is represented in a format that can be directly edited and/or rendered by conventional application programs, such as digital content creation (DCC) tools. For example, the constructed 3D model may be represented as a triangular surface mesh (with arbitrary topology), a set of 2D textures representing spatially-varying material parameters, and an environment map. Furthermore, the constructed 3D model may be included in 3D scenes and interacts realistically with other objects.Type: GrantFiled: May 30, 2022Date of Patent: April 23, 2024Assignee: NVIDIA CorporationInventors: Carl Jacob Munkberg, Jon Niklas Theodor Hasselgren, Tianchang Shen, Jun Gao, Wenzheng Chen, Alex John Bauld Evans, Thomas Müller-Höhne, Sanja Fidler
-
Patent number: 11966838Abstract: In various examples, a machine learning model—such as a deep neural network (DNN)—may be trained to use image data and/or other sensor data as inputs to generate two-dimensional or three-dimensional trajectory points in world space, a vehicle orientation, and/or a vehicle state. For example, sensor data that represents orientation, steering information, and/or speed of a vehicle may be collected and used to automatically generate a trajectory for use as ground truth data for training the DNN. Once deployed, the trajectory points, the vehicle orientation, and/or the vehicle state may be used by a control component (e.g., a vehicle controller) for controlling the vehicle through a physical environment. For example, the control component may use these outputs of the DNN to determine a control profile (e.g., steering, decelerating, and/or accelerating) specific to the vehicle for controlling the vehicle through the physical environment.Type: GrantFiled: May 10, 2019Date of Patent: April 23, 2024Assignee: NVIDIA CorporationInventors: Urs Muller, Mariusz Bojarski, Chenyi Chen, Bernhard Firner