Patents Assigned to NVidia
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Publication number: 20250086896Abstract: In various examples, systems and methods are disclosed relating to neural networks for three-dimensional (3D) scene representations and modifying the 3D scene representations. In some implementations, a diffusion model can be configured to modify selected portions of 3D scenes represented using neural radiance fields, without painting back in content of the selected portions that was originally present. A first view of the neural radiance fields can be inpainted to remove a target feature from the first view, and used as guidance for updating the neural radiance field so that the target feature can be realistically removed from various second views of the neural radiance fields while context is retained outside of the selected portions.Type: ApplicationFiled: September 12, 2023Publication date: March 13, 2025Applicant: NVIDIA CorporationInventors: Or LITANY, Sanja FIDLER, Cho-Ying WU, Huan LING, Zan GOJCIC, Riccardo DE LUTIO, Sameh KHAMIS
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Publication number: 20250083309Abstract: In various examples, systems and methods are disclosed relating to geometric fabrics for accelerated policy learning and sim-to-real transfer in robotics systems, platforms, and/or applications. For example, a system can provide an input indicative of a goal pose for a robot to a model to cause the model to generate an output, the output representing a plurality of points along a path for movement of the robot to the goal pose; and generate one or more control signals for operation of the robot based at least on the plurality of points along the path and a policy corresponding to one or more criteria for the operation of the robot. In examples, the system can provide the one or more control signals to the robot to cause the robot to move toward the goal pose.Type: ApplicationFiled: April 25, 2024Publication date: March 13, 2025Applicant: NVIDIA CorporationInventors: Nathan Donald RATLIFF, Karl VAN WYK, Ankur HANDA, Viktor MAKOVIICHUK, Yijie GUO, Jie XU, Tyler LUM, Balakumar SUNDARALINGAM, Jingzhou LIU
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Publication number: 20250085973Abstract: Apparatuses, systems, and techniques to execute CUDA programs. In at least one embodiment, one or more software kernels are caused to indicate one or more dependencies among two or more software kernels. In at least one embodiment, one or more software kernels are performed based on one or more kernel dependencies.Type: ApplicationFiled: September 11, 2023Publication date: March 13, 2025Applicant: NVIDIA CorporationInventors: Ze Long, Stephen Anthony Bernard Jones, Pradeep Moorthy, Mark Theng
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Patent number: 12248788Abstract: Distributed shared memory (DSMEM) comprises blocks of memory that are distributed or scattered across a processor (such as a GPU). Threads executing on a processing core local to one memory block are able to access a memory block local to a different processing core. In one embodiment, shared access to these DSMEM allocations distributed across a collection of processing cores is implemented by communications between the processing cores. Such distributed shared memory provides very low latency memory access for processing cores located in proximity to the memory blocks, and also provides a way for more distant processing cores to also access the memory blocks in a manner and using interconnects that do not interfere with the processing cores' access to main or global memory such as hacked by an L2 cache.Type: GrantFiled: March 10, 2022Date of Patent: March 11, 2025Assignee: NVIDIA CorporationInventors: Prakash Bangalore Prabhakar, Gentaro Hirota, Ronny Krashinsky, Ze Long, Brian Pharris, Rajballav Dash, Jeff Tuckey, Jerome F. Duluk, Jr., Lacky Shah, Luke Durant, Jack Choquette, Eric Werness, Naman Govil, Manan Patel, Shayani Deb, Sandeep Navada, John Edmondson, Greg Palmer, Wish Gandhi, Ravi Manyam, Apoorv Parle, Olivier Giroux, Shirish Gadre, Steve Heinrich
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Patent number: 12249589Abstract: Apparatus for flattening a warped ball grid array (BGA) package, including a first plate having a first surface and opposite second surface and a second plate having a first surface and opposite second surface. The first surface of the first plate and the first surface of the second plate oppose each other with a gap there-between. The gap houses the warped BGA package there-in, the warped BGA package including a package substrate with solder balls attached to a device mounting surface of the package substrate to form a BGA thereon. The gap adjustable by changing the position of the first plate or of the second plate such that a pushing force is applicable to the warped BGA package. A method of manufacturing a flattened BGA package and computer having a circuit that include the flatted BGA package are also disclosed.Type: GrantFiled: June 6, 2022Date of Patent: March 11, 2025Assignee: NVIDIA CorporationInventors: Dongji Xie, Joe Hai, Zhongming Wu, Ernesto A. Opiniano
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Patent number: 12248203Abstract: In an embodiment, a modular augmented reality display is provided that incorporates prescription eyewear that can be used separately by the wearer. In an embodiment, an image is generated from a removable display attached to the eyewear and directed into the edge of a prescription lens, which acts as a waveguide. The image is internally reflected within the prescription lens, and is directed to the wearer by an image combiner embedded within the prescription lens. In an embodiment, the augmented reality display includes a wearable belt pouch that includes a battery and support electronics connected to the eyewear so that the weight on the eyewear is reduced.Type: GrantFiled: April 6, 2023Date of Patent: March 11, 2025Assignee: NVIDIA CorporationInventors: Jonghyun Kim, Benjamin Boudaoud, Michael Stengel, Josef Bo Spjut, Morgan Samuel McGuire
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Patent number: 12249619Abstract: An integrated circuit including a chip substrate having an upper isolation layer with a pad thereon and a coil located below the pad, where, in a dimension perpendicular to a surface of the chip substrate, a perimeter of the coil overlaps with a perimeter of the pad.Type: GrantFiled: April 25, 2022Date of Patent: March 11, 2025Assignee: NVIDIA CorporationInventor: Jedrzej Wyczynski
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Patent number: 12246718Abstract: Embodiments of the present disclosure relate to encoding of junction area information in map data. In particular, the encoding may include organizing vehicle paths that traverse through a junction area according to path groups and organizing contentions that influence behavior of vehicles traveling along the vehicle paths according to contention groups. In addition, the encoding may include generating direction data structures that associate respective path groups with one or more of the contention groups. In these or other embodiments, the map data that corresponds to the junction area may be updated with direction data structures.Type: GrantFiled: June 17, 2022Date of Patent: March 11, 2025Assignee: NVIDIA CORPORATIONInventors: Russell Chreptyk, Matthew Ashman, Andy Campbell, Tharun Battula, Vaibhav Thukral
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Patent number: 12249022Abstract: A Displaced Micro-mesh (DMM) primitive enables high complexity geometry for ray and path tracing while minimizing the associated builder costs and preserving high efficiency. A structured, hierarchical representation implicitly encodes vertex positions of a triangle micro-mesh based on a barycentric grid, and enables microvertex displacements to be encoded efficiently (e.g., as scalars linearly interpolated between minimum and maximum triangle surfaces). The resulting displaced micro-mesh primitive provides a highly compressed representation of a potentially vast number of displaced microtriangles that can be stored in a small amount of space. Improvements in ray tracing hardware permit automatic processing of such primitive for ray-geometry intersection testing by ray tracing circuits without requiring intermediate reporting to a shader.Type: GrantFiled: September 16, 2022Date of Patent: March 11, 2025Assignee: NVIDIA CorporationInventors: John Burgess, Gregory Muthler, Nikhil Dixit, Henry Moreton, Yury Uralsky, Magnus Andersson, Marco Salvi, Christoph Kubisch
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Patent number: 12248319Abstract: In various examples, systems and methods are disclosed that preserve rich spatial information from an input resolution of a machine learning model to regress on lines in an input image. The machine learning model may be trained to predict, in deployment, distances for each pixel of the input image at an input resolution to a line pixel determined to correspond to a line in the input image. The machine learning model may further be trained to predict angles and label classes of the line. An embedding algorithm may be used to train the machine learning model to predict clusters of line pixels that each correspond to a respective line in the input image. In deployment, the predictions of the machine learning model may be used as an aid for understanding the surrounding environment—e.g., for updating a world model—in a variety of autonomous machine applications.Type: GrantFiled: June 23, 2023Date of Patent: March 11, 2025Assignee: NVIDIA CorporationInventors: Minwoo Park, Xiaolin Lin, Hae-Jong Seo, David Nister, Neda Cvijetic
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Patent number: 12248392Abstract: In various examples, a diagnostic circuit is connected to a target system to automatically trigger the target system to enter a diagnostic mode. The diagnostic circuit receives diagnostic data from the target system when the target system performs a diagnostic operation in the diagnostic mode.Type: GrantFiled: February 28, 2022Date of Patent: March 11, 2025Assignee: NVIDIA CorporationInventors: Padmanabham Patki, Jue Wu, Chung-Hong Lai, Laurent Dahan, Marc Delvaux, Chiang Hsu
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Patent number: 12249163Abstract: In various examples, object fence corresponding to objects detected by an ego-vehicle may be used to determine overlap of the object fences with lanes on a driving surface. A lane mask may be generated corresponding to the lanes on the driving surface, and the object fences may be compared to the lanes of the lane mask to determine the overlap. Where an object fence is located in more than one lane, a boundary scoring approach may be used to determine a ratio of overlap of the boundary fence, and thus the object, with each of the lanes. The overlap with one or more lanes for each object may be used to determine lane assignments for the objects, and the lane assignments may be used by the ego-vehicle to determine a path or trajectory along the driving surface.Type: GrantFiled: April 19, 2021Date of Patent: March 11, 2025Assignee: NVIDIA CorporationInventors: Josh Abbott, Miguel Sainz Serra, Zhaoting Ye, David Nister
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Patent number: 12248881Abstract: According to an aspect of an embodiment, a method may include obtaining multiple sets of camera images and light detection and ranging (LIDAR) point clouds along a track within a geographic sector of a map. The method may include applying a learning model to the camera images to characterize objects within the camera images within classes of objects to generate segmented images. The method may additionally include mapping the sets of camera images and the LIDAR point clouds to three dimensional points of the geographic sector of the map. The method may also include projecting the three dimensional points onto the segmented images to obtain corresponding classes for the three dimensional points of the geographic sector of the map.Type: GrantFiled: September 14, 2023Date of Patent: March 11, 2025Assignee: NVIDIA CORPORATIONInventors: Lin Yang, Xiaqing Wu
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Patent number: 12249048Abstract: One embodiment of the present invention sets forth a technique for generating data. The technique includes sampling from a first distribution associated with the score-based generative model to generate a first set of values. The technique also includes performing one or more denoising operations via the score-based generative model to convert the first set of values into a first set of latent variable values associated with a latent space. The technique further includes converting the first set of latent variable values into a generative output.Type: GrantFiled: February 25, 2022Date of Patent: March 11, 2025Assignee: NVIDIA CORPORATIONInventors: Arash Vahdat, Karsten Kreis, Jan Kautz
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Publication number: 20250079062Abstract: A magnetic inductor core forms a three-dimensional figure eight pattern. An upper member of the core forms an upper half of the figure eight pattern, a lower member of the core forms a lower half of the figure eight pattern, and central portions of the upper and lower members are separated from one another in a depth dimension by a main gap that passes transversely through the core from left to right sides of the figure eight pattern. The upper and lower members are joined at top and bottom sides of the figure eight pattern by core members that extend in the depth dimension between the upper and lower members. Coupled inductor components are be formed using the core such that magnetic flux associated with electrical current flowing in the inductor windings follows the figure eight pattern of the core in opposite directions, producing a flux cancelation effect inside the core.Type: ApplicationFiled: February 29, 2024Publication date: March 6, 2025Applicant: NVIDIA CorporationInventors: Youssef Elasser, Sudhir Kudva, Mostafa Mosa
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Publication number: 20250077624Abstract: In various examples, systems and methods are disclosed relating to graph generation. One system includes one or more processing circuits configured to receive a first data structure including one or more relationships between a plurality of components. The one or more processing circuits are further configured to encode, using a predefined function, a second data structure determined based on the first data structure to generate a noisy representation of the second data structure. The one or more processing circuits are further configured to decode, using one or more models, the first data structure based on feature extraction and pattern analysis of the noisy representation.Type: ApplicationFiled: November 20, 2023Publication date: March 6, 2025Applicant: NVIDIA CorporationInventors: Marc LAW, Karsten Julian KREIS, Haggai MARON
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Publication number: 20250081349Abstract: A secure electronic component assembly is described herein for ensuring the physical integrity of an integrated circuit (IC). The secure electronic component assembly may comprise a printed circuit board (PCB), an integrated circuit (IC) mounted on the PCB, and an underfill material disposed between the IC and the PCB. The underfill material comprises a detection agent that is configured to change a state of the IC in response to exposure to an external environment, wherein the change in the state of the IC is indicative of a tamper condition.Type: ApplicationFiled: September 5, 2023Publication date: March 6, 2025Applicant: NVIDIA CORPORATIONInventors: Elad Mentovich, Dongji Xie, Ron Chao, Ryan Albright
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Publication number: 20250079344Abstract: A secure electronic component assembly is described herein for ensuring the physical integrity of an integrated circuit (IC). The secure electronic component assembly may comprise a printed circuit board (PCB), an integrated circuit (IC) mounted on the PCB, and a security chip that is operatively coupled to the IC. The IC may comprise a plurality of solder balls operatively coupled thereto and configured for physical and electrical connection between the IC and the PCB. The security chip is configured to detect a potential tampering of the IC.Type: ApplicationFiled: September 5, 2023Publication date: March 6, 2025Applicant: NVIDIA CORPORATIONInventors: Elad Mentovich, Dongji Xie, Ron Chao
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Publication number: 20250079063Abstract: A magnetic inductor core forms a three-dimensional figure eight pattern. An upper member of the core forms an upper half of the figure eight pattern, a lower member of the core forms a lower half of the figure eight pattern, and central portions of the upper and lower members are separated from one another in a depth dimension by a main gap that passes transversely through the core from left to right sides of the figure eight pattern. The upper and lower members are joined at top and bottom sides of the figure eight pattern by core members that extend in the depth dimension between the upper and lower members. Coupled inductor components are be formed using the core such that magnetic flux associated with electrical current flowing in the inductor windings follows the figure eight pattern of the core in opposite directions, producing a flux cancelation effect inside the core.Type: ApplicationFiled: March 28, 2024Publication date: March 6, 2025Applicant: NVIDIA CorporationInventors: Youssef Elasser, Sudhir Kudva, Mostafa Mosa
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Publication number: 20250080755Abstract: In various examples, systems, devices and methods are disclosed relating to enhancing the efficiency and reducing the delay of error resilience in multimedia communication systems. The systems, devices and methods can include a computer system determining a sliding frame window (or a sliding reference window) for a video stream. The size of the sliding frame window represents a minimum separation between reference frames and corresponding inter frames. The computer system can encode a plurality of video frames of the video stream according to the size of the sliding frame window, such that a separation between any pair of video frames of the plurality of video frames including a reference frame and a corresponding inter-frame is greater than or equal to the size of the sliding frame window.Type: ApplicationFiled: August 30, 2023Publication date: March 6, 2025Applicant: NVIDIA CorporationInventors: Fateh SABEH, Mohamadreza MARANDIAN HAGH, Varun VIJAYA KUMAR, Shridhar MAJALI, Harsh MANIAR