Abstract: A method for transmitting data advantageously reduces cross-talk in high-speed data transmission. The method comprises receiving an input data word, encoding the input data word into a code word, and driving the code word on to an interconnect for transmission. The code word is generating using a balanced coding scheme, and the interconnect is a single-ended, twisted-wire interposer interconnect. A receiver circuit decodes the code word to generate an output data word.

Abstract: A method for displaying a near-eye light field display (NELD) image is disclosed. The method comprises determining a pre-filtered image to be displayed, wherein the pre-filtered image corresponds to a target image. It further comprises displaying the pre-filtered image on a display. Subsequently, it comprises producing a near-eye light field after the pre-filtered image travels through a microlens array adjacent to the display, wherein the near-eye light field is operable to simulate a light field corresponding to the target image. Finally, it comprises altering the near-eye light field using at least one converging lens, wherein the altering allows a user to focus on the target image at an increased depth of field at an increased distance from an eye of the user and wherein the altering increases spatial resolution of said target image.

Abstract: In one embodiment, a micro-processing system includes a hardware structure disposed on a processor core. The hardware structure includes a plurality of entries, each of which are associated with portion of code and a translation of that code which can be executed to achieve substantially equivalent functionality. The hardware structure includes a redirection array that enables, when referenced, execution to be redirected from a portion of code to its counterpart translation. The entries enabling such redirection are maintained within or evicted from the hardware structure based on usage information for the entries.

Abstract: Optimizing computing device application profiles. Receiving, from power-user computing devices, a set of user-based application profiles, each application profile including one or more device parameter settings associated with an application operable to run on the devices. Evaluating the set on an optimization server computer with an electronic processor operable to: calculate if a count of the profiles of the set exceeds a predefined minimum threshold count; calculate a variance for one of the device parameter settings of the set, if the count exceeds the minimum threshold count; calculate if the variance is below a predefined maximum threshold variance; calculate an optimal value for the one of the device parameter settings, if the variance is below the maximum threshold variance; and storing, in computer-readable storage media of the optimization server computer, the optimal value in a recommended set. Publishing the recommended set towards end-user computing devices configured to run the application.

Abstract: A graphics effect data structure and method of use thereof. One embodiment of the graphics effect data structure is embodied in an effect processing system, including: (1) a memory configured to store an effect data structure that describes a graphics effect implemented by a plurality of passes and shader code modules contained in the effect data structure, (2) a graphics processing unit (GPU) operable to render the graphics effect according to a shader program based on the shader code modules, assembled according to the plurality of passes, and (3) a central processing unit (CPU) configured to execute an application that employs the graphics effect and to gain access to the effect data structure during run time, at which time the shader program is passed to the GPU for processing.

Abstract: Embodiments related to re-dispatching an instruction selected for re-execution from a buffer upon a microprocessor re-entering a particular execution location after runahead are provided. In one example, a microprocessor is provided. The example microprocessor includes fetch logic, one or more execution mechanisms for executing a retrieved instruction provided by the fetch logic, and scheduler logic for scheduling the retrieved instruction for execution. The example scheduler logic includes a buffer for storing the retrieved instruction and one or more additional instructions, the scheduler logic being configured, upon the microprocessor re-entering at a particular execution location after runahead, to re-dispatch, from the buffer, an instruction that has been previously dispatched to one of the execution mechanisms.

Abstract: A power supply system. The power system includes a power supply controller for supplying a control signal. The power system also includes a plurality of MOSFET drivers controlled by the control signal. The power system also includes a plurality of power channels. Each of the power channels includes a plurality of MOSFETs that is controlled by a corresponding MOSFET driver. The plurality of power channels is configured to generate a plurality of power signals, wherein the control signal controls delivery of the plurality of power signals through each of the power channels.

Abstract: A method of noise filter parameter adaptation, the method comprising receiving a current video frame comprising a plurality of pixels. A table lookup is performed, using current statistical values associated with the current video frame. Noise filter parameters are adapted, based on current lighting conditions as determined from the performed table lookup. The current lighting conditions correspond to the current statistical values. The current video frame is noise filtered as defined by the adapted noise filter parameters.

Abstract: Various embodiments relating to reducing memory bandwidth consumed by a continuous scan display screen are provided. In one embodiment, scoring criteria are applied to a reference image of a first image format having a first bit depth to generate an image conversion score. The scoring criteria are based on a histogram of one or more characteristics of the reference image. If the image conversion score is greater than a threshold value, then the reference image is converted to a modified image of a second image format having a second bit depth less than the first bit depth, and the modified image is scanned onto the continuous scan display screen. If the image conversion score is less than the threshold value, then the reference image is scanned onto the continuous scan display screen.

Abstract: Image scaling techniques, in accordance with embodiments of the present technology, include directionally interpolating blocks of pixel data of an image, sharpening the directional interpolated blocks of pixel data, and optionally clamping the sharpened, directional interpolated blocks of pixel data.

Abstract: Remotely synchronizing data communicated in an electronic computing system. Ordered writing of a data set of discrete data packets (data) and a following associated semaphore packet (semaphore) from a source electronic device (source) to a bridge interface device (bridge). Relaxed writing of the data set from the bridge to discrete target memory addresses (targets) of a data-consuming electronic device (consumer), wherein the order of the data and the semaphore written to the targets is different than the order of the data and semaphore written with the ordered writing. Monitoring, by the consumer, the relaxed writing of the semaphore to one of the targets. Issuing a synchronization command to the bridge upon detection of the semaphore having been written to the one target. Sending a synchronization confirmation reply from the bridge after all of the data has been written to the targets.

Abstract: Techniques are disclosed for tracking memory page accesses in a unified virtual memory system. An access tracking unit detects a memory page access generated by a first processor for accessing a memory page in a memory system of a second processor. The access tracking unit determines whether a cache memory includes an entry for the memory page. If so, then the access tracking unit increments an associated access counter. Otherwise, the access tracking unit attempts to find an unused entry in the cache memory that is available for allocation. If so, then the access tracking unit associates the second entry with the memory page, and sets an access counter associated with the second entry to an initial value. Otherwise, the access tracking unit selects a valid entry in the cache memory; clears an associated valid bit; associates the entry with the memory page; and initializes an associated access counter.

Abstract: One embodiment of the present invention includes a microcontroller coupled to a memory management unit (MMU). The MMU is coupled to a page table included in a physical memory, and the microcontroller is configured to perform one or more virtual memory operations associated with the physical memory and the page table. In operation, the microcontroller receives a page fault generated by the MMU in response to an invalid memory access via a virtual memory address. To remedy such a page fault, the microcontroller performs actions to map the virtual memory address to an appropriate location in the physical memory. By contrast, in prior-art systems, a fault handler would typically remedy the page fault. Advantageously, because the microcontroller executes these tasks locally with respect to the MMU and the physical memory, latency associated with remedying page faults may be decreased. Consequently, overall system performance may be increased.

Abstract: An aspect of the present invention proposes a solution to allow low-cost flat panel displays without light guides to maintain a high quality image display via enhancement of pixel data to account for non uniform brightness. According to one embodiment, each pixel of a display is mapped to the brightness (intensity) of illumination that reaches the pixel. Regional pixel gains are calculated and applied on a per pixel basis to compensate for the non-uniform brightness across the screen. According to such an embodiment, even low cost flat panel displays experiencing non-uniform brightness can be used to render high quality images.

Abstract: A method for linking information related to a computer crash. The method includes establishing a network of computing resources communicatively coupled to a network, wherein each computing resource is associated with a corresponding hardware configuration capable of executing and displaying at least one application, wherein each of the network of computing resources is associated with a globally unique identifier (GUID). The method includes receiving configuration information relating to the network of computing resources. The method includes receiving a crash report of a crash occurring on a crashed computing system within the network of computing resources. The method includes extracting a GUID from the crash report, wherein the GUID identifies said crashed computing resource. The method includes determining configuration information for the crashed computing resource, and correlating the configuration information with the crash information.

Abstract: In a system according to one embodiment of the present disclosure, the system comprises a first device, a second device, a communications link, and a memory. The memory stores instructions that when executed by the system perform a method of communications link training. This method comprises requesting a speed change to a second speed for the first device communicating with the second device at a first speed via the communications link. A saved set of parameters are accessed for at least one of the first device and the second device. A first training cycle is performed for the first device and the second device at the second speed using the saved set of parameters for the at least one of the first device and second device. The reuse of parameters from a previous successful equalization training cycle reduces the time required to perform equalization training.

Abstract: A method for rotating macro-blocks of a frame of a video stream. A degree of rotation for the video stream is accessed. A macro-block of the video stream is accessed. The macro-block is rotated according to the degree of rotation. The macro-block is repositioned to a new position within the frame, wherein the new position is based on the degree of rotation.

Abstract: Methods of providing in-game virtual split screens with peer-to-peer video conferencing are described for use in online gaming, for instance. In one approach, a live video stream, a live audio stream, and a player viewpoint are sent from a first computer system for receipt by a second computer system. The first and second computer systems concurrently execute the online game. The live video stream, the in-game video stream, and locally rendered in-game content are combined to create a composite video stream, and the live audio stream, the in-game audio stream, and locally generated in-game audio are combined to create a composite audio stream. The composite video stream and the composite audio stream are operable to be presented at the second computer system in real-time.

Abstract: A monitor display system includes a computing device that is coupled to a collection of dissimilar monitors and a display manager that is coupled to the computing device. The display manager has an image generator that generates an image for the collection of dissimilar monitors and also has a pixel density normalizer that is coupled to the image generator and provides an alignment of the image across the collection of dissimilar monitors. A method of managing a display image is also included.

Abstract: Mitigating external influences on long signal lines. In accordance with an embodiment of the present invention, a column of a memory array includes first and second transistors configured to pull up the bit line of the column. The column includes a third transistor configured to selectively pull up the bit line of the column responsive to a level of the inverted bit line of the column and a fourth transistor configured to selectively pull up the inverted bit line of the column responsive to a level of the bit line of the column. The column further includes fifth and sixth transistors configured to selectively pull up the bit line and inverted bit line of the column responsive to the clamp signal and a seventh transistor configured to selectively couple the bit line of the column and the inverted bit line of the column responsive to the clamp signal.