Abstract: One embodiment of the present invention includes techniques for a first processing unit to perform an atomic operation on a memory page shared with a second processing unit. The memory page is associated with a page table entry corresponding to the first processing unit. Before executing the atomic operation, an MMU included in the first processing unit evaluates an atomic permission bit that is included in the page table entry. If the MMU determines that the atomic permission bit is inactive, then the two processing units coordinate to change the permission status of the memory page. As part of the status change, the atomic permission bit in the page table entry is activated. Subsequently, the first processing unit performs the atomic operation uninterrupted by the second processing unit. Advantageously, coordinating the processing unit via the atomic permission bit ensures the proper and efficient execution of the atomic operation.

Abstract: Methods for operating a small cell in a discontinued reception (DRX) mode include maintaining the small cell in a discontinuous transmission (DTX) mode during a first time period having a plurality of first time slots. The methods include transmitting common reference signals in a predetermined number of second time slots prior to the first time slots and in a predetermined number of third time slots following commencement of the first time slots. The methods include discontinuing transmission of the common reference signals and common channel signals if mobile devices are in a discontinuous reception mode during the first time period. The methods include discontinuing transmission of the common reference signals during a predetermined number of fourth time slots following commencement of the first time period if there is no dedicated common transmission to the mobile devices.

Abstract: An active component of an integrated voltage regulator (IVR) circuit is deployed within an IC device for regulating an operating voltage thereof. An interposer interconnects the IC device with a power source. A passive inductive component of the IVR circuit is deployed upon a surface of the IC device or the interposer. The inductive component has a magnetic core and a winding (e.g., wire-bond), wound about the magnetic core.

Abstract: Systems and methods for generating high dynamic images from interleaved Bayer array data with high spatial resolution and reduced sampling artifacts. Bayer array data are demosaiced into components of the YUV color space before deinterleaving. The Y component and the UV components can be derived from the Bayer array data through demosiac convolution processes. A respective convolution is performed between a convolution kernel and a set of adjacent pixels of the Bayer array that are in the same color channel. A convolution kernel is selected based the mosaic pattern of the Bayer array and the color channels of the set of adjacent pixels. The Y data and UV data are deinterleaved and interpolated into frames of short exposure and long exposures in the second color space. The short exposure and long exposure frames are then blended and converted back to a RGB frame representing a high dynamic range image.

Abstract: An integrated circuit package includes a packaging substrate, which has an electrically conductive grid formed on a dielectric layer, and an integrated circuit die electrically coupled to the electrically conductive grid at one or more locations. In this embodiment, the electrically conductive grid includes a plurality of electrically conductive portions, wherein each portion is electrically coupled to at least one other portion, and a plurality of void regions that are electrically non-contiguous and substantially free of electrically conductive material. One advantage of the integrated circuit package is that a packaging substrate that is reduced in thickness, and therefore rigidity, can still maintain planarity during operation.

Abstract: One embodiment of the present invention sets forth a technique for performing aggregation operations across multiple threads that execute independently. Aggregation is specified as part of a barrier synchronization or barrier arrival instruction, where in addition to performing the barrier synchronization or arrival, the instruction aggregates (using reduction or scan operations) values supplied by each thread. When a thread executes the barrier aggregation instruction the thread contributes to a scan or reduction result, and waits to execute any more instructions until after all of the threads have executed the barrier aggregation instruction. A reduction result is communicated to each thread after all of the threads have executed the barrier aggregation instruction and a scan result is communicated to each thread as the barrier aggregation instruction is executed by the thread.

Abstract: In one embodiment of the present invention, a streaming multiprocessor (SM) uses a tree of nodes to manage threads. Each node specifies a set of active threads and a program counter. Upon encountering a conditional instruction that causes an execution path to diverge, the SM creates child nodes corresponding to each of the divergent execution paths. Based on the conditional instruction, the SM assigns each active thread included in the parent node to at most one child node, and the SM temporarily discontinues executing instructions specified by the parent node. Instead, the SM concurrently executes instructions specified by the child nodes. After all the divergent paths reconverge to the parent path, the SM resumes executing instructions specified by the parent node. Advantageously, the disclosed techniques enable the SM to execute divergent paths in parallel, thereby reducing undesirable program behavior associated with conventional techniques that serialize divergent paths across thread groups.

Abstract: A low noise amplifier includes a first input transistor coupled to an input signal and a second input transistor coupled to the input signal. The low noise amplifier also includes a first output transistor, coupled between the first input transistor and a first carrier aggregation load, configured to connect the first input transistor to the first carrier aggregation load. Additionally, the low noise amplifier includes a second output transistor, coupled between the first input transistor and a second carrier aggregation load, configured to connect the first input transistor to the second carrier aggregation load. Further, the low noise amplifier includes a third output transistor, coupled between the second input transistor and the second carrier aggregation load, configured to connect the second input transistor to the second carrier aggregation load. Also included are a method of operating a low noise amplifier and an extended carrier low noise amplifier.

Abstract: A power subsystem is configured to manage the maximum power usage of a computer subsystem. A power detector determines when power usage approaches the maximum capability of the power supply. The power detector generates a signal that corresponds to power usage. A controller then applies the signal to the system voltage regulator as a secondary regulation function such that the output voltage is reduced in a manner that supports maximum operating voltage while limiting power usage to within the capability of the power supply. The controller may configure the signal to implement the secondary regulation function as a modification of the feedback voltage, the reference voltage, or the current feedback of the regulator. As a result the subsystem causes the computer subsystem to operate at an optimum point on the voltage-current curve of the power supply.

Abstract: Embodiments of the approaches disclosed herein include a subsystem that includes an access tracking mechanism configured to monitor access operations directed to a first memory and a second memory. The access tracking mechanism detects an access operation generated by a processor for accessing a first memory page residing on the second memory. The access tracking mechanism further determines that the first memory page is included in a first subset of memory pages residing on the second memory. The access tracking mechanism further locates, within a reference vector, a reference bit that corresponds to the first memory page, and sets the reference bit. One advantage of the present invention is that memory pages in a hybrid system migrate as needed to increase overall memory performance.

Abstract: An approach is provided for enabling power reduction in floating-point operations. In one example, a system receives floating-point numbers of a fused multiply-add instruction. The system determines the fused multiply-add instruction does not require compliance with a standard of precision for floating-point numbers. The system generates gating signals for an integrated circuit that is configured to perform operations of the fused multiply-add instruction. The system then sends the gating signals to the integrated circuit to turn off a plurality of logic gates included in the integrated circuit.

Abstract: One embodiment of the present invention sets forth a technique for estimating a head pose of a user. The technique includes acquiring depth data associated with a head of the user and initializing each particle included in a set of particles with a different candidate head pose. The technique further includes performing one or more optimization passes that include performing at least one iterative closest point (ICP) iteration for each particle and performing at least one particle swarm optimization (PSO) iteration. Each ICP iteration includes rendering the three-dimensional reference model based on the candidate head pose associated with the particle and comparing the three-dimensional reference model to the depth data. Each PSO iteration comprises updating a global best head pose associated with the set of particles and modifying at least one candidate head pose. The technique further includes modifying a shape of the three-dimensional reference model based on depth data.

Abstract: A method for driving a display panel having a variable refresh rate is disclosed. The method comprises detecting a condition that results in a charge accumulation in the display panel using an accumulated difference in time duration between frames of positive polarity and frames of negative polarity received from an image source. The DC imbalance is a result of a frame pattern comprising alternating frames of differing polarities, wherein frames of positive polarity within the frame pattern are of a different time duration than frames of negative polarity, and wherein the frame pattern results in an accumulation of charge in pixels of the display panel. The method also comprises correcting for the charge accumulation by disrupting the frame pattern.

Abstract: One embodiment sets forth a technique for time-multiplexed communication for transmitting command and address information between a controller and a multi-port memory device over a single connection. Command and address information for each port of the multi-port memory device is time-multiplexed within the controller to produce a single stream of commands and addresses for different memory requests. The single stream of commands and addresses is transmitted by the controller to the multi-port memory device where the single stream is demultiplexed to generate separate streams of commands and addresses for each port of the multi-port memory device.

Abstract: A system including one or more input interface drivers, an input dispatcher, one or more applications, a system compositor and one or more output interface drivers. The input interface driver receives input events. The input dispatcher is modified to dispatch a current input event to a corresponding application after receiving an indication that a display image based upon a previous input event has been posted to an output interface driver. The corresponding application renders a new display image based upon the current input event. The system compositor posts the new display image to the output interface driver. The system compositor is also modified to send an indication to the input dispatcher that the new display image has been posted to the output interface driver. The system iteratively performs the process to latch the dispatching of input events to the display flip.

Abstract: A subsystem configured to implement an analog to digital converter that includes a high speed comparator with an embedded reference voltage level that functions as a calibrated threshold. A calibration element applies power to a reference voltage system. The calibration element then selects a differential analog voltage and applies the differential analog voltage to the inputs of the comparator. A digitally coded signal then configures an array of switches that connect complements of integrated resistors to each input of the comparator so that the switching point of the comparator occurs coincident with the applied differential analog reference voltage, nulling out the effect of the applied differential analog voltage and comparator errors. The calibration element then removes power from the reference voltage system. As a result, the comparator is configured with an embedded threshold that equals the differential analog reference voltage.

Abstract: A computer system has a touch sensitive display screen within a housing and a touch sensor, which is coupled to a bus. A processor and a memory are coupled to the bus. The housing has a channel for receiving and storing a stylus. A sensor is disposed adjacent to the channel. The sensor interacts with the stylus through the Hall effect caused by a magnet within the stylus and is thus operable for detecting a presence or absence of the stylus without physical contact therewith. The memory has an application which, when executed on the processor, automatically performs one or more stylus related software functions upon a reported absence of the stylus from the channel. One of the software functions includes palm detection rejection with respect to data from the touch sensor. Another function includes display of a GUI displaying a listing of applications that are based on stylus data entry modes. Another function includes setting up OS modes designed for accurate operation of stylus data entry.

Abstract: Various embodiments of microprocessors and methods of operating a microprocessor during runahead operation are disclosed herein. One example method of operating a microprocessor includes identifying a runahead-triggering event associated with a runahead-triggering instruction and, responsive to identification of the runahead-triggering event, entering runahead operation and inserting the runahead-triggering instruction along with one or more additional instructions in a queue. The example method also includes resuming non-runahead operation of the microprocessor in response to resolution of the runahead-triggering event and re-dispatching the runahead-triggering instruction along with the one or more additional instructions from the queue to the execution logic.

Abstract: Embodiments of the present invention are operable to generate a set of weights derived through crowdsourcing procedures for use in automatically performing white balancing operations on images captured by a digital camera system. Embodiments of the present invention are operable to generate a set of images which are illuminated with known and different illuminants. Using crowdsourcing procedures, embodiments of the present invention gather user feedback concerning which images from the set of images adjusted by the known illuminants are considered to be the most aesthetically pleasing. Images selected by the users are then stored within a database of selected images. Using a learning engine, embodiments of the present invention may then produce a set of weights based on the user selected images for use in determining a likely illuminant when performing automatic white balancing operations performed on the camera system.

Abstract: Embodiments of the claimed subject matter are directed to methods and systems that allow tracking and accounting of wear and other aging effects in integrated circuits and products which include integrated circuits over time, and the dynamic adjustment of operating conditions to increase or decrease wear in response to the accumulated wear relative to the expected wear during the lifetime of the circuit and/or product.