Patents Assigned to NVidia
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Patent number: 11704863Abstract: A hardware-based traversal coprocessor provides acceleration of tree traversal operations searching for intersections between primitives represented in a tree data structure and a ray. The primitives may include triangles used in generating a virtual scene. The hardware-based traversal coprocessor is configured to properly handle numerically challenging computations at or near edges and/or vertices of primitives and/or ensure that a single intersection is reported when a ray intersects a surface formed by primitives at or near edges and/or vertices of the primitives.Type: GrantFiled: April 8, 2022Date of Patent: July 18, 2023Assignee: NVIDIA CorporationInventors: Samuli Laine, Tero Karras, Timo Aila, Robert Ohannessian, William Parsons Newhall, Jr., Greg Muthler, Ian Kwong, Peter Nelson, John Burgess
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Patent number: 11704860Abstract: One embodiment of a computer-implemented method for processing ray tracing operations in parallel includes receiving a plurality of rays and a corresponding set of importance sampling instructions for each ray included in the plurality of rays for processing, wherein each ray represents a path from a light source to at least one point within a three-dimensional (3D) environment, and each corresponding set of importance sampling instruction is based at least in part on one or more material properties associated with at least one surface of at least one object included in the 3D environment; assigning each ray included in the plurality of rays to a different processing core included in a plurality of processing cores; and for each ray included in the plurality of rays, causing the processing core assigned to the ray to execute the corresponding set of importance sampling instructions on the ray to generate a direction for a secondary ray that is produced when the ray intersects a surface of an object within theType: GrantFiled: May 14, 2021Date of Patent: July 18, 2023Assignee: NVIDIA CorporationInventors: Robert A. Alfieri, Peter S. Shirley
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Patent number: 11703348Abstract: A semi-public blockchain maintained on one or more nodes in a map cloud platform comprises data for maintaining a global map of a predetermined geographic area. The blockchain also comprises a plurality of data records, where each data record is associated with an update to a global map. When a message associated with a map update to the global map is received, the nodes of the blockchain determine a consensus by evaluating the map update, where the evaluating comprises performing a plurality of proofs including a proof of location, a proof of iterations, a proof of physical delivery and a proof of safety. When consensus is attained and the map update is validated, a data record associated with the map update is generated and added to the blockchain with a timestamp and a link to prior data records in the blockchain.Type: GrantFiled: January 5, 2021Date of Patent: July 18, 2023Assignee: NVIDIA CorporationInventor: Justyna Zander
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Patent number: 11704167Abstract: Approaches in accordance with various embodiments can reduce scheduling delays due to concurrent processing requests, as may involve VSyncs in multi-streaming systems. The software synchronization signals can be staggered relative to each other by offsetting an initial synchronization signal. These software synchronization signals can be readjusted over time such that each synchronization signal maintains the same relative offset, as may be with respect to other applications or containers.Type: GrantFiled: August 15, 2022Date of Patent: July 18, 2023Assignee: Nvidia CorporationInventors: Bimal Poddar, Donghan Ryu, Michael Gold, Samuel Reed Koser, Xiao Bo Zhao Zhang
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Patent number: 11700713Abstract: An adapter plate and a fastening system for fastening a manifold to a rack in a datacenter is disclosed. The adapter plate is associated with the manifold and has holes to receive buttons in configurable positions. The configurable positions enable the buttons to mate with keyholes of a bracket of the rack in order to fasten the manifold to the bracket.Type: GrantFiled: July 8, 2020Date of Patent: July 11, 2023Assignee: NVIDIA CorporationInventors: Harold Miyamura, Jeremy Rodriguez, Ali Heydari
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Patent number: 11700402Abstract: A performance metrics of a receiver is obtained using frames of an application hosted by a server that are received via a network. The one or more performance metrics include information indicative of a current occupancy of a frame buffer corresponding to the receiver and information indicative of a target occupancy of the frame buffer corresponding to the receiver. The frame buffer of the receiver is used to queue frames of the application for display. A frame rate associated with rendering at least one next frame of the application is adjusted using the one or more performance metrics of the receiver to control population of the frame buffer. Subsequent frames of the application hosted by the server are rendered using the adjusted frame rate. Upon rendering the subsequent frames, the server sends the subsequent frames to the receiver for display.Type: GrantFiled: March 25, 2022Date of Patent: July 11, 2023Assignee: Nvidia CorporationInventors: Rouslan Dimitrov, Viktor Grigoryevich Vandanov, Sau Yan Keith Li, James Howard, Scott Phillip Cutler
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Patent number: 11698869Abstract: The subject application relates to computing an authentication tag for partial transfers scheduled across multiple direct memory access (DMA) engines. Apparatuses, systems, and techniques are described for computing an authentication tag for a data transfer when the data transfer is scheduled as partial transfers across a specified number of direct memory access (DMA) engines. An orchestration circuit stores partial authentication tags, computed by the DMA engines, and corresponding adjustment exponents during one or more rounds in which the partial transfers are scheduled and processed by the specified number of DMA engines. During a last round, a combined authentication tag can be computed based on the partial authentication tags and the corresponding adjustment exponents stored by the orchestration circuit during the rounds.Type: GrantFiled: March 10, 2022Date of Patent: July 11, 2023Assignee: NVIDIA CorporationInventors: Vaishali Kulkarni, Naveen Cherukuri, Raymond Wong, Adam Hendrickson, Gobikrishna Dhanuskodi, Wish Gandhi
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Patent number: 11698272Abstract: An end-to-end system for data generation, map creation using the generated data, and localization to the created map is disclosed. Mapstreams—or streams of sensor data, perception outputs from deep neural networks (DNNs), and/or relative trajectory data—corresponding to any number of drives by any number of vehicles may be generated and uploaded to the cloud. The mapstreams may be used to generate map data—and ultimately a fused high definition (HD) map—that represents data generated over a plurality of drives. When localizing to the fused HD map, individual localization results may be generated based on comparisons of real-time data from a sensor modality to map data corresponding to the same sensor modality. This process may be repeated for any number of sensor modalities and the results may be fused together to determine a final fused localization result.Type: GrantFiled: August 31, 2020Date of Patent: July 11, 2023Assignee: NVIDIA CorporationInventors: Michael Kroepfl, Amir Akbarzadeh, Ruchi Bhargava, Vaibhav Thukral, Neda Cvijetic, Vadim Cugunovs, David Nister, Birgit Henke, Ibrahim Eden, Youding Zhu, Michael Grabner, Ivana Stojanovic, Yu Sheng, Jeffrey Liu, Enliang Zheng, Jordan Marr, Andrew Carley
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Patent number: 11700419Abstract: In various examples, a media stream may be received by a re-encode system that may leverage a recode engine to convert (e.g., at an interval, based on a request, etc.) an inter-frame associated with the media stream to an intra-frame. The intra-frame may be converted from the inter-frame using parameters or other information associated with and received with the media stream. The converted intra-frame may be merged into an updated segment of the media stream in place of the original inter-frame to enable storage of the updated segment—or a portion thereof—for later use.Type: GrantFiled: February 28, 2022Date of Patent: July 11, 2023Assignee: NVIDIA CorporationInventors: Olivier Lapicque, Srinivas Anne
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Patent number: 11699662Abstract: In accordance with the disclosure, one or both semiconductor dies in a face-to-face arrangement may include a probe pad layer formed on a face of the die to allow the die to be individually tested prior to assembly of the dies. Thus, faulty dies may be discarded individually so they are not included in a composite semiconductor device, thereby increasing device yields. The probe pad layer also allows dies to be matched so that a composite semiconductor device achieves desired performance, which may further increase device yields. In some embodiments, the probe pads of the probe pad layer formed on the face of the die may be used to individually test the die, and may remain inactive, or inert, during operation of the composite semiconductor device.Type: GrantFiled: January 23, 2020Date of Patent: July 11, 2023Assignee: NVIDIA CorporationInventors: Joseph Greco, Joseph Minacapelli
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Patent number: 11693753Abstract: In various examples, permanent faults in hardware component(s) and/or connections to the hardware component(s) of a computing platform may be predicted before they occur using in-system testing. As a result of this prediction, one or more remedial actions may be determined to enhance the safety of the computing platform (e.g., an autonomous vehicle). A degradation rate of a performance characteristic associated with the hardware component may be determined, detected, and/or computed by monitoring values of performance characteristics over time using fault testing.Type: GrantFiled: October 15, 2019Date of Patent: July 4, 2023Assignee: NVIDIA CorporationInventors: Gunaseelan Ponnuvel, Ashish Karandikar
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Patent number: 11695601Abstract: A system includes a transmitter to transmit a set of bits associated with signaling having one or more levels. The system includes a receiver coupled to the transmitter, the receiver to receive the set of bits and generate a first plurality of digital values, each digital value generated at a first timing value and a plurality of reference voltages, the reference voltage incremented based at least in part on generating a digital value of the first plurality of digital values. The receiver is to generate a second plurality of digital values at a second timing value and the plurality of reference voltages, the first timing value incremented to the second timing value based at least in part on generating the first plurality of digital values. The system includes a controller to determine an amplitude associated with each the first and second plurality of digital values.Type: GrantFiled: August 13, 2021Date of Patent: July 4, 2023Assignee: Nvidia CorporationInventors: Sunil Rao Sudhakaran, Arash Zargaran-Yazd, Santhosh Kumar Gude, Seema Kumar
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Patent number: 11693667Abstract: Systems and methods are provided for efficiently performing processing intensive operations, such as those involving large volumes of data, that enable accelerated processing time of these operations. In at least one embodiment, a system includes a graphics processor unit (GPU) including a memory and a plurality of cores. The plurality of cores perform a plurality of data analytics operations on a respectively allocated portion of a dataset, each of the plurality of cores using only the memory to store data input for each of the plurality of data analytics operations performed by the plurality of cores. The data storage for the plurality of data analytics operations performed by the plurality of cores is also provided solely by the memory.Type: GrantFiled: March 11, 2022Date of Patent: July 4, 2023Assignee: NVIDIA CorporationInventors: Joshua Patterson, Leeann Chau Tuyet Dang, Keith Jason Kraus, Allan Rabbitt Enemark, Frank Joseph Eaton, Bradley Stuart Rees, Michael Evan Wendt, Mark Jason Harris
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Patent number: 11694643Abstract: In various examples, a low-latency variable backlight liquid crystal display (LCD) system is disclosed. The LCD system may reduce latency and video lag by performing an analysis of peak pixel values within subsets of pixels using a rendering device, prior to transmitting the frame to a display device for display. As a result, the display device may receive the peak pixel value data prior to or concurrently with the frame data, and may begin updating the backlight settings of the display without having to wait for a substantial portion of the frame to be received. In this way, the LCD system may avoid the full frame delay of conventional systems, allowing the LCD system to more reliably support high-performance applications such as gaming.Type: GrantFiled: June 2, 2021Date of Patent: July 4, 2023Assignee: NVIDIA CorporationInventors: Jens Roever, Gerrit Ary Slavenburg, Robert Jan Schutten
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Patent number: 11693470Abstract: In various examples, a voltage monitor may determine whether the voltage supplied to at least one component of a computing system is safe using two sets of thresholds—e.g., a high-frequency over-voltage (OV) threshold, a high-frequency under-voltage (UV) threshold, a low-frequency OV threshold, and a low-frequency UV threshold. A high-frequency voltage error detector may compare the supplied or input voltage to the high-frequency OV and UV thresholds and a low-frequency voltage error detector that may filter the supplied voltage to remove or reduce noise and then may compare the filtered voltage to the low-frequency OV and UV thresholds. Upon detecting a voltage error, a safety monitor may cause a change to an operating state of the at least one component.Type: GrantFiled: June 28, 2022Date of Patent: July 4, 2023Assignee: NVIDIA CorporationInventors: Ashok Srinivasan, Gokul Ryan Santhirakumaran
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Patent number: 11694072Abstract: A method and system are disclosed for training a model that implements a machine-learning algorithm. The technique utilizes latent descriptor vectors to change a multiple-valued output problem into a single-valued output problem and includes the steps of receiving a set of training data, processing, by a model, the set of training data to generate a set of output vectors, and adjusting a set of model parameters and component values for at least one latent descriptor vector in the plurality of latent descriptor vectors based on the set of output vectors. The set of training data includes a plurality of input vectors and a plurality of desired output vectors, and each input vector in the plurality of input vectors is associated with a particular latent descriptor vector in a plurality of latent descriptor vectors. Each latent descriptor vector comprises a plurality of scalar values that are initialized prior to training the model.Type: GrantFiled: November 29, 2017Date of Patent: July 4, 2023Assignee: NVIDIA CorporationInventors: Tero Tapani Karras, Timo Oskari Aila, Samuli Matias Laine
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Patent number: 11689750Abstract: Embodiments of the present disclosure relate to workload-based dynamic throttling of video processing functions. Systems and methods are disclosed that dynamically throttle video processing and/or streaming based on a workload. Live video is captured from one or more sources (e.g., cameras) and stored. The video is then provided to a video processing engine and a video streaming engine. The video processing engine may perform one or more operations such as object detection, object tracking, and object classification to produce characterization data (e.g., bounding boxes, object trajectories, alerts, object labels, object counts, boundary crossings, intersection highlighting, etc.). System resource usage and performance of the video processing and streaming are monitored to produce workload data (e.g., metrics). Based on the policies and the workload data, the video streaming and/or processing is dynamically reconfigured by adjusting parameters provided to the video streaming and processing engines.Type: GrantFiled: October 7, 2021Date of Patent: June 27, 2023Assignee: NVIDIA CorporationInventors: Bhanu Nagendra Pisupati, Rahul Maruti Bhagwat, Rohit Ramesh Vaswani, David Ung, Joonhwa Shin
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Patent number: 11688074Abstract: In various examples, a background of an object may be modified to generate a training image. A segmentation mask may be generated and used to generate an object image that includes image data representing the object. The object image may be integrated into a different background and used for data augmentation in training a neural network. Data augmentation may also be performed using hue adjustment (e.g., of the object image) and/or rendering three-dimensional capture data that corresponds to the object from selected views. Inference scores may be analyzed to select a background for an image to be included in a training dataset. Backgrounds may be selected and training images may be added to a training dataset iteratively during training (e.g., between epochs). Additionally, early or late fusion nay be employed that uses object mask data to improve inferencing performed by a neural network trained using object mask data.Type: GrantFiled: September 30, 2020Date of Patent: June 27, 2023Assignee: NVIDIA CorporationInventors: Nishant Puri, Sakthivel Sivaraman, Rajath Shetty, Niranjan Avadhanam
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Patent number: 11688042Abstract: Various approaches are disclosed to temporally and spatially filter noisy image data—generated using one or more ray-tracing effects—in a graphically rendered image. Rather than fully sampling data values using spatial filters, the data values may be sparsely sampled using filter taps within the spatial filters. To account for the sparse sampling, locations of filter taps may be jittered spatially and/or temporally. For filtering efficiency, a size of a spatial filter may be reduced when historical data values are used to temporally filter pixels. Further, data values filtered using a temporal filter may be clamped to avoid ghosting. For further filtering efficiency, a spatial filter may be applied as a separable filter in which the filtering for a filter direction may be performed over multiple iterations using reducing filter widths, decreasing the chance of visual artifacts when the spatial filter does not follow a true Gaussian distribution.Type: GrantFiled: July 15, 2021Date of Patent: June 27, 2023Assignee: NVIDIA CorporationInventors: Shiqiu Liu, Jacopo Pantaleoni
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Patent number: 11687133Abstract: A computing device comprises: a heat sink that has a plurality of cooling fins and a vapor chamber; one or more heat-generating electronic devices that are thermally coupled to the vapor chamber; and at least one cooling fan configured to direct cooling air across the plurality of cooling fins, wherein a first fin included in the plurality of cooling fins and a second fin included in the plurality of cooling fins form a first air passage that has a first air inlet opening and a first air outlet opening, and wherein the first fin is adjacent to the second fin, and a first distance between the first fin and the second fin proximate to the first air inlet opening is less than a second distance between the first fin and the second fin proximate to the first air outlet opening.Type: GrantFiled: December 3, 2020Date of Patent: June 27, 2023Assignee: NVIDIA CorporationInventors: Amit Kulkarni, Gabriele Gorla, Andrew Bell, Boris Landwehr