Abstract: Disclosed are apparatuses, systems, and techniques to render images depicting light interacting with media that have volume attenuation, using optimized spectral rendering that emulates rendering of the media in tristimulus color rendering schemes.
Abstract: A transceiver circuit includes a receiver front end utilizing a ring oscillator, and a transmitter front end utilizing a pass-gate circuit in a first feedback path across a last-stage driver circuit. The transceiver circuit provides low impedance at low frequency and high impedance at high frequency, and desirable peaking behavior.
Abstract: A method dynamically selects one of a first sampling order and a second sampling order for a ray trace of pixels in a tile where the selection is based on a motion vector for the tile. The sampling order may be a bowtie pattern or an hourglass pattern.
Type:
Application
Filed:
March 15, 2023
Publication date:
August 24, 2023
Applicant:
NVIDIA Corp.
Inventors:
Johan Pontus Andersson, Jim Nilsson, Tomas Guy Akenine-Möller
Abstract: A static random access memory (SRAM) or other bit-storing cell arrangement includes memory cells and a hierarchical bitline structure including local bitlines for subsets of the memory banks and a global bitline spanning the subsets. A keeper circuit for the global bitline is replaced by bias circuitry on output transistors of the memory cells.
Type:
Application
Filed:
February 23, 2022
Publication date:
August 24, 2023
Applicant:
NVIDIA Corp.
Inventors:
Lalit Gupta, Stefan P. Sywyk, Andreas Jon Gotterba, Jesse Wang
Abstract: A three-dimensional (3D) model of an object is recovered from two-dimensional (2D) images of the object. Each image in the set of 2D images includes the object captured from a different camera position and deformations of a base mesh that defines the 3D model may be computed corresponding to each image. The 3D model may also include a texture map that represents the lighting and material properties of the 3D model. Recovery of the 3D model relies on analytic antialiasing to provide a link between pixel colors in the 2D images and geometry of the 3D model. A modular differentiable renderer design yields high performance by leveraging existing, highly optimized hardware graphics pipelines to reconstruct the 3D model. The differential renderer renders images of the 3D model and differences between the rendered images and reference images are propagated backwards through the rendering pipeline to iteratively adjust the 3D model.
Type:
Grant
Filed:
February 15, 2021
Date of Patent:
August 22, 2023
Assignee:
NVIDIA Corporation
Inventors:
Samuli Matias Laine, Janne Johannes Hellsten, Tero Tapani Karras, Yeongho Seol, Jaakko T. Lehtinen, Timo Oskari Aila
Abstract: The disclosure presents a technique for utilizing ray tracing to produce high quality visual scenes with shadows while minimizing computing costs. The disclosed technique can lower the number of rays needed for shadow region rendering and still maintain a targeted visual quality for the scene. In one example, a method for denoising a ray traced scene is disclosed that includes: (1) applying a pixel mask to a data structure of data from the scene, wherein the applying uses the scene at full resolution and pixels at the edge of a depth boundary change are identified using the pixel mask, (2) generating a penumbra mask using the data structure, (3) adjusting HitT values in the packed data buffer utilizing the penumbra mask, and (4) denoising the scene by reducing scene noise in the data of the data structure with adjusted HitT values.
Abstract: Packet flows between a transmitter and a receiver in an unreliable and unordered switched packet network may be established as a result of receiving a second packet comprising a second memory operation on a memory address. The transmission of memory load command packets followed by memory store command packets in the packet flow may be serialized, and a synchronization operation may be executed between the transmitter and the receiver when a packet count at the receiver satisfies a number of data packets in the packet flow.
Type:
Application
Filed:
February 17, 2022
Publication date:
August 17, 2023
Applicant:
NVIDIA Corp.
Inventors:
Hans Eberle, Larry Robert Dennison, John Martin Snyder
Abstract: Apparatuses, systems, and techniques to generate blue noise masks for real-time image rendering and enhancement. In at least one embodiment, a vector-valued noise mask is generated and applied to one or more images to generate one or more enhanced images for image processing (e.g., real-time image rendering). In at least one embodiment, the noise mask includes vector values per pixel and is able to handle the temporal domain (e.g., add time to the spatial domain) to improve image quality when rendering images over multiple frames.
Abstract: In examples, threads of a schedulable unit (e.g., a warp or wavefront) of a parallel processor may be used to sample visibility of pixels with respect to one or more light sources. The threads may receive the results of the sampling performed by other threads in the schedulable unit to compute a value that indicates whether a region corresponds to a penumbra (e.g., using a wave intrinsic function). Each thread may correspond to a respective pixel and the region may correspond to the pixels of the schedulable unit. A frame may be divided into the regions with each region corresponding to a respective schedulable unit. In denoising ray-traced shadow information, the values for the regions may be used to avoid applying a denoising filter to pixels of regions that are outside of a penumbra while applying the denoising filter to pixels of regions that are within a penumbra.
Abstract: In various examples, shader bindings may be recorded in a shader binding table that includes shader records. Geometry of a 3D scene may be instantiated using object instances, and each may be associated with a respective set of the shader records using a location identifier of the set of shader records in memory. The set of shader records may represent shader bindings for an object instance under various predefined conditions. One or more of these predefined conditions may be implicit in the way the shader records are arranged in memory (e.g., indexed by ray type, by sub-geometry, etc.). For example, a section selector value (e.g., a section index) may be computed to locate and select a shader record based at least in part on a result of a ray tracing query (e.g., what sub-geometry was hit, what ray type was traced, etc.).
Type:
Grant
Filed:
July 15, 2021
Date of Patent:
August 15, 2023
Assignee:
NVIDIA Corporation
Inventors:
Martin Stich, Ignacio Llamas, Steven Parker
Abstract: Manufacturers perform tests on chips before the chips are shipped to customers. However, defects can occur on a chip after the manufacturer testing and when the chips are used in a system or device. The defects can occur due to aging or the environment in which the chip is employed and can be critical; especially when the chips are used in systems such as autonomous vehicles. To verify the structural integrity of the IC during the lifetime of the product, an in-system test (IST) is disclosed. The IST enables self-testing mechanisms for an IC in working systems. The IST mechanisms provide structural testing of the ICs when in a functional system and at a manufacturer's level of testing. Unlike ATE tests that are running on a separate environment, the IST provides the ability to go from a functional world view to a test mode.
Abstract: Apparatuses, systems, and techniques to detect faults in processing pipelines are described. One accelerator circuit includes a fixed-function circuit that performs an operation corresponding to a layer of a neural network. The fixed-function circuit includes a set of homogeneous processing units and a fault scanner circuit. The fault scanner circuit includes an additional homogeneous processing unit to scan each processing unit of the set for functional faults in a sequence.
Type:
Grant
Filed:
July 13, 2021
Date of Patent:
August 15, 2023
Assignee:
NVIDIA Corporation
Inventors:
Yilin Zhang, Shangang Zhang, Yan Zhou, Qifei Fan
Abstract: In various examples, a gaze direction of a user's eyes may be tracked and synced with perception data of the vehicle to determine POIs that the user is interested in. In some examples, POIs may be stored as waypoints in a waypoint catalog or store and included as part of a map. As a user is driving in a vehicle down a roadway, a system onboard the vehicle may access the map to determine locations of the vehicle, and may reference the waypoint catalog to determine the POIs that the vehicle passes. Using an advertiser name, contact information, an advertisement image, advertiser website information, links to additional content, etc. relating to each waypoint, a log of the passed POIs may be stored for access by the user.
Abstract: According to an aspect of an embodiment, operations may comprise receiving a point cloud representing a region. The operations may also comprise identifying a cluster of points in the point cloud having a higher intensity than points outside the cluster of points. The operations may also comprise determining a bounding box around the cluster of points. The operations may also comprise identifying a traffic sign within the bounding box. The operations may also comprise projecting the bounding box to coordinates of an image of the region captured by a camera. The operations may also comprise employing a deep learning model to classify a traffic sign type of the traffic sign in a portion of the image within the projected bounding box. The operations may also comprise storing information regarding the traffic sign and the traffic sign type in a high definition (HD) map of the region.
Type:
Grant
Filed:
June 18, 2020
Date of Patent:
August 15, 2023
Assignee:
NVIDIA CORPORATION
Inventors:
Derek Thomas Miller, Yu Zhang, Lin Yang
Abstract: The disclosure provides processors that are configured to perform dynamic programming according to an instruction, a method for configuring a processor for dynamic programming according to an instruction and a method of computing a modified Smith Waterman algorithm employing an instruction for configuring a parallel processing unit. In one example, the method for configuring includes: (1) receiving, by execution cores of the processor, an instruction that directs the execution cores to compute a set of recurrence equations employing a matrix, (2) configuring the execution cores, according to the set of recurrence equations, to compute states for elements of the matrix, and (3) storing the computed states for current elements of the matrix in registers of the execution cores, wherein the computed states are determined based on the set of recurrence equations and input data.
Abstract: Apparatuses, systems, and techniques determine a set of grasp poses that would allow a robot to successfully grasp an object that is proximate to at least one additional object. In at least one embodiment, the set of grasp poses is modified based on a determination that at least one of the grasp poses in the set of grasp poses would interfere with at least one additional object that is proximate to the object.
Type:
Grant
Filed:
June 26, 2020
Date of Patent:
August 15, 2023
Assignee:
NVIDIA Corporation
Inventors:
Arsalan Mousavian, Clemens Eppner, Dieter Fox, Adithyavairavan Murali
Abstract: Methods, systems, and devices are provided herein for providing a visually guided topology wiring scheme. As described herein, after determining that a first end of a cable has been inserted at a first port of a first peer device, a wiring application may reference a topology file to identify a second port of a second peer device with which the first peer device is intended to have a link. Subsequently, the wiring application may activate an indicator associated with the second port to mimic an indicator associated with the first port. For example, the wiring application may cause both indicators associated with each port to flash according to a same or similar flashing pattern, to produce or illuminate at a similar or identical color (e.g., approximately the same color), to flash at approximately a same rate, or by substantially synchronizing a flashing of each indicator.
Abstract: Various embodiments include a parallel processing computer system that detects memory errors as a memory client loads data from memory and disables the memory client from storing data to memory, thereby reducing the likelihood that the memory error propagates to other memory clients. The memory client initiates a stall sequence, while other memory clients continue to execute instructions and the memory continues to service memory load and store operations. When a memory error is detected, a specific bit pattern is stored in conjunction with the data associated with the memory error. When the data is copied from one memory to another memory, the specific bit pattern is also copied, in order to identify the data as having a memory error.
Type:
Grant
Filed:
July 12, 2021
Date of Patent:
August 8, 2023
Assignee:
NVIDIA CORPORATION
Inventors:
Naveen Cherukuri, Saurabh Hukerikar, Paul Racunas, Nirmal Raj Saxena, David Charles Patrick, Yiyang Feng, Abhijeet Ghadge, Steven James Heinrich, Adam Hendrickson, Gentaro Hirota, Praveen Joginipally, Vaishali Kulkarni, Peter C. Mills, Sandeep Navada, Manan Patel, Liang Yin
Abstract: Various embodiments include techniques for reducing high-frequency interference to a wireless communications channel emanating from a wired communications channel. The techniques are directed towards an application that determines a mode of a particular wired communications channel. The mode of the wired communications channel is indicative of the frequency ranges at which the interference is generated. The application further determines a frequency and/or bandwidth of the wireless communications channel. The application selects a slew rate that reduces the high frequency interference from the wired communications channel at the frequency and/or bandwidth of the wireless communications channel. The application thereby optimizes the reduction of the high-frequency interference from the particular wired communications channel to the particular wireless communications channel.