Patents Assigned to NVidia
  • Patent number: 11594014
    Abstract: According to an aspect of an embodiment, operations may comprise obtaining a first point cloud that includes a first point. The operations also comprises obtaining a second point cloud that is a copy of the first point cloud and that includes a second point that is a copy of the first point. The operations also comprises moving the second point cloud with respect to the first point cloud according to a first vector. The operations also comprises identifying a closest point of the first point cloud that is closest to the second point of the second point cloud. The operations also comprises determining a second vector between the closest point and the second point. The operations also comprises determining a measure of usefulness of the first point based on the first vector and the second vector. The operations also comprises indicating the measure of usefulness of the first point.
    Type: Grant
    Filed: June 22, 2020
    Date of Patent: February 28, 2023
    Assignee: NVIDIA CORPORATION
    Inventors: Di Zeng, Mengxi Wu
  • Patent number: 11595152
    Abstract: Embodiments of the present disclosure relate to a binary clustered forward error correction encoding scheme. Systems and methods are disclosed that define binary clustered encodings of the media packets from which forward error correction (FEC) packets are computed. The different encodings specify which media packets in a frame are used to compute each FEC packet (a frame includes M media packets). The different encodings may be defined based on the quantity of media packets in a frame, M?floor(2N), where each bit of the binary representation of N is associated with a different cluster pair encoding of the media packets. Each cluster pair includes a cluster for which the bit=0 and a cluster for which the bit=1. Computing FEC packets using at least two cluster pair encodings provides redundancy for each media packet, thereby improving media packet recovery rates.
    Type: Grant
    Filed: November 4, 2021
    Date of Patent: February 28, 2023
    Assignee: NVIDIA Corporation
    Inventors: Shridhar Majali, Harsh Chandresh Maniar, Reza Marandian Hagh
  • Patent number: 11594962
    Abstract: This disclosure relates to current flattening circuits for an electrical load. The current flattening circuits incorporate randomize various parameters to add noise onto the supply current. This added noise may act to reduce the signal to noise ratio in the supply current, increasing the difficulty of identifying a computational artifact signal from power rail noise.
    Type: Grant
    Filed: January 20, 2022
    Date of Patent: February 28, 2023
    Assignee: NVIDIA CORP.
    Inventors: Sudhir Shrikantha Kudva, Nikola Nedovic, Sanquan Song
  • Patent number: 11593344
    Abstract: A computer-implemented method may include monitoring an age of a tile of a map, where the map includes multiple tiles including the tile. The method may also include, based on the age exceeding a threshold age, determining that the tile of the map is to be updated, and receiving a location indicator from a vehicle. The method may additionally include transmitting an update message to a vehicle traversing a track within the tile as indicated by the location indicator, where the update message includes instructions to cause the vehicle to gather and submit sensor data to a computing system. The method may also include receiving the sensor data from the vehicle, and updating the tile of the map based on the received sensor data.
    Type: Grant
    Filed: July 1, 2020
    Date of Patent: February 28, 2023
    Assignee: NVIDIA CORPORATION
    Inventors: François Joseph Bailly, Kevin Yang
  • Patent number: 11593988
    Abstract: In various examples, transmittance may be computed using a power-series expansion of an exponential integral of a density function. A term of the power-series expansion may be evaluated as a combination of values of the term for different orderings of samples in the power-series expansion. A sample may be computed from a combination of values at spaced intervals along the function and a discontinuity may be compensated for based at least on determining a version of the function that includes an alignment of a first point with a second point of the function. Rather than arbitrarily or manually selecting a pivot used to expand the power-series, the pivot may be computed as an average of values of the function. The transmittance estimation may be computed from the power-series expansion using a value used to compute the pivot (for a biased estimate) or using all different values (for an unbiased estimate).
    Type: Grant
    Filed: February 8, 2021
    Date of Patent: February 28, 2023
    Assignee: NVIDIA Corporation
    Inventors: Eugene d″Eon, Jan Novak, Jacopo Pantaleoni, Niko Markus Kettunen
  • Patent number: 11593290
    Abstract: In various examples, a VPU and associated components may be optimized to improve VPU performance and throughput. For example, the VPU may include a min/max collector, automatic store predication functionality, a SIMD data path organization that allows for inter-lane sharing, a transposed load/store with stride parameter functionality, a load with permute and zero insertion functionality, hardware, logic, and memory layout functionality to allow for two point and two by two point lookups, and per memory bank load caching capabilities. In addition, decoupled accelerators may be used to offload VPU processing tasks to increase throughput and performance, and a hardware sequencer may be included in a DMA system to reduce programming complexity of the VPU and the DMA system. The DMA and VPU may execute a VPU configuration mode that allows the VPU and DMA to operate without a processing controller for performing dynamic region based data movement operations.
    Type: Grant
    Filed: August 2, 2021
    Date of Patent: February 28, 2023
    Assignee: NVIDIA Corporation
    Inventors: Ahmad Itani, Yen-Te Shih, Jagadeesh Sankaran, Ravi P Singh, Ching-Yu Hung
  • Patent number: 11592828
    Abstract: In various examples, motifs, watermarks, and/or signature inputs are applied to a deep neural network (DNN) to detect faults in underlying hardware and/or software executing the DNN. Information corresponding to the motifs, watermarks, and/or signatures may be compared to the outputs of the DNN generated using the motifs, watermarks and/or signatures. When a the accuracy of the predictions are below a threshold, or do not correspond to the expected predictions of the DNN, the hardware and/or software may be determined to have a fault—such as a transient, an intermittent, or a permanent fault. Where a fault is determined, portions of the system that rely on the computations of the DNN may be shut down, or redundant systems may be used in place of the primary system. Where no fault is determined, the computations of the DNN may be relied upon by the system.
    Type: Grant
    Filed: January 16, 2020
    Date of Patent: February 28, 2023
    Assignee: NVIDIA Corporation
    Inventors: Richard Bramley, Philip Payman Shirvani, Nirmal Saxena
  • Patent number: 11593001
    Abstract: A VPU and associated components include a min/max collector, automatic store predication functionality, a SIMD data path organization that allows for inter-lane sharing, a transposed load/store with stride parameter functionality, a load with permute and zero insertion functionality, hardware, logic, and memory layout functionality to allow for two point and two by two point lookups, and per memory bank load caching capabilities. In addition, decoupled accelerators are used to offload VPU processing tasks to increase throughput and performance, and a hardware sequencer is included in a DMA system to reduce programming complexity of the VPU and the DMA system. The DMA and VPU executes a VPU configuration mode that allows the VPU and DMA to operate without a processing controller for performing dynamic region based data movement operations.
    Type: Grant
    Filed: August 2, 2021
    Date of Patent: February 28, 2023
    Assignee: NVIDIA Corporation
    Inventors: Ching-Yu Hung, Ravi P Singh, Jagadeesh Sankaran, Yen-Te Shih, Ahmad Itani
  • Patent number: 11590989
    Abstract: According to an aspect of an embodiment, operations may comprise receiving a plurality of frame sets generated while navigating a local environment, receiving an occupancy map (OMap) representation of the local environment, for each of the plurality of frame sets, generating, using the OMap representation, one or more instances each comprising a spatial cluster of neighborhood 3D points generated from a 3D sensor scan of the local environment, and classifying each of the instances as dynamic or static, tracking instances classified as dynamic across the plurality of frame sets using a tracking algorithm, assigning a single instance ID to tracked instances classified as dynamic across the plurality of frame sets, estimating a bounding box for each of the instances in each of the plurality of frame sets, and employing the instances as ground truth data in a training of one or more deep learning classifiers.
    Type: Grant
    Filed: July 2, 2020
    Date of Patent: February 28, 2023
    Assignee: NVIDIA CORPORATION
    Inventor: Chirag Majithia
  • Patent number: 11590929
    Abstract: Systems and methods are disclosed herein for implementation of a vehicle command operation system that may use multi-modal technology to authenticate an occupant of the vehicle to authorize a command and receive natural language commands for vehicular operations. The system may utilize sensors to receive data indicative of a voice command from an occupant of the vehicle. The system may receive second sensor data to aid in the determination of the corresponding vehicular operation in response to the received command. The system may retrieve authentication data for the occupants of the vehicle. The system authenticates the occupant to authorize a vehicular operation command using a neural network based on at least one of the first sensor data, the second sensor data, and the authentication data. Responsive to the authentication, the system may authorize the operation to be performed in the vehicle based on the vehicular operation command.
    Type: Grant
    Filed: May 5, 2020
    Date of Patent: February 28, 2023
    Assignee: NVIDIA Corporation
    Inventors: Sumit Bhattacharya, Jason Conrad Roche, Niranjan Avadhanam
  • Patent number: 11594006
    Abstract: There are numerous features in video that can be detected using computer-based systems, such as objects and/or motion. The detection of these features, and in particular the detection of motion, has many useful applications, such as action recognition, activity detection, object tracking, etc. The present disclosure provides a neural network that learns motion from unlabeled video frames. In particular, the neural network uses the unlabeled video frames to perform self-supervised hierarchical motion learning. The present disclosure also describes how the learned motion can be used in video action recognition.
    Type: Grant
    Filed: August 20, 2020
    Date of Patent: February 28, 2023
    Assignee: NVIDIA CORPORATION
    Inventors: Xiaodong Yang, Xitong Yang, Sifei Liu, Jan Kautz
  • Publication number: 20230053487
    Abstract: Various implementations of a current flattening circuit are disclosed, including those utilizing a feedback current regulator, a feedforward current regulator, and a constant current source.
    Type: Application
    Filed: October 13, 2022
    Publication date: February 23, 2023
    Applicant: NVIDIA Corp.
    Inventors: Nikola Nedovic, Sudhir Shrikantha Kudva
  • Patent number: 11588608
    Abstract: A device includes a transmitter to transmit serialized data within a differential direct-current (DC) signal over a differential output line, a multiplexer circuit coupled to the transmitter, and a calibration circuit coupled between the differential output line, a multi-phase clock, and the multiplexer circuit. The multiplexer circuit is to select the serialized data from ones of multiple input lines according to a multi-phase clock and pass the selected serialized data to the transmitter. The serialized data includes a calibration bit pattern. The calibration circuit is to capture and digitize the differential DC signal into a digital stream, measure an error value from the digital stream that is associated with distortion based on the calibration bit pattern, convert the error value into a gradient value, and correct one or more phases of the multi-phase clock to compensate for the distortion based on the gradient value.
    Type: Grant
    Filed: August 4, 2021
    Date of Patent: February 21, 2023
    Assignee: NVIDIA Corporation
    Inventors: Venkatraman Natarajan, Arif Amin, Dai Dai, Olakanmi Oluwole, Shashank Mahajan
  • Patent number: 11582431
    Abstract: Apparatuses, systems, and techniques to receive, at one or more processor associated with an image signal processing (ISP) pipeline, a compressed image generated by an image sensor, wherein the compressed image is captured at a first bit-depth associated with the image sensor and is compressed to a second bit-depth that is lower than the first bit-depth, and wherein the ISP is associated with a third bit-depth that is lower than the first bit-depth and higher than the second bit-depth; and decompress the compressed image according to a power curve to generate a partially decompressed image having the third bit-depth, wherein a plurality of regions of the partially decompressed image are decompressed at separate decompression amounts based on a corresponding pixel value of each region of the plurality of regions.
    Type: Grant
    Filed: August 30, 2021
    Date of Patent: February 14, 2023
    Assignee: NVIDIA CORPORATION
    Inventors: Animesh Khemka, Sean Midthun Pieper
  • Patent number: 11579925
    Abstract: A parallel processing unit (PPU) can be divided into partitions. Each partition is configured to operate similarly to how the entire PPU operates. A given partition includes a subset of the computational and memory resources associated with the entire PPU. Software that executes on a CPU partitions the PPU for an admin user. A guest user is assigned to a partition and can perform processing tasks within that partition in isolation from any other guest users assigned to any other partitions. Because the PPU can be divided into isolated partitions, multiple CPU processes can efficiently utilize PPU resources.
    Type: Grant
    Filed: September 5, 2019
    Date of Patent: February 14, 2023
    Assignee: NVIDIA CORPORATION
    Inventors: Jerome F. Duluk, Jr., Gregory Scott Palmer, Jonathon Stuart Ramsey Evans, Shailendra Singh, Samuel H. Duncan, Wishwesh Anil Gandhi, Lacky V. Shah, Eric Rock, Feiqi Su, James Leroy Deming, Alan Menezes, Pranav Vaidya, Praveen Joginipally, Timothy John Purcell, Manas Mandal
  • Patent number: 11579852
    Abstract: System and method of compiling a program having a mixture of host code and device code to enable Profile Guided Optimization (PGO) for device code execution. An exemplary integrated compiler can compile source code programmed to be executed by a host processor (e.g., CPU) and a co-processor (e.g., a GPU) concurrently. The compilation can generate an instrumented executable code which includes: profile instrumentation counters for the device functions; and instructions for the host processor to allocate and initialize device memory for the counters and to retrieve collected profile information from the device memory to generate instrumentation output. The output is fed back to the compiler for compiling the source code a second time to generate optimized executable code for the device functions defined in the source code.
    Type: Grant
    Filed: July 27, 2020
    Date of Patent: February 14, 2023
    Assignee: NVIDIA Corporation
    Inventors: Hariharan Sandanagobalane, Sean Lee, Vinod Grover
  • Patent number: 11579629
    Abstract: In various examples, a sequential deep neural network (DNN) may be trained using ground truth data generated by correlating (e.g., by cross-sensor fusion) sensor data with image data representative of a sequences of images. In deployment, the sequential DNN may leverage the sensor correlation to compute various predictions using image data alone. The predictions may include velocities, in world space, of objects in fields of view of an ego-vehicle, current and future locations of the objects in image space, and/or a time-to-collision (TTC) between the objects and the ego-vehicle. These predictions may be used as part of a perception system for understanding and reacting to a current physical environment of the ego-vehicle.
    Type: Grant
    Filed: July 17, 2019
    Date of Patent: February 14, 2023
    Assignee: NVIDIA Corporation
    Inventors: Yue Wu, Pekka Janis, Xin Tong, Cheng-Chieh Yang, Minwoo Park, David Nister
  • Patent number: 11580395
    Abstract: A latent code defined in an input space is processed by the mapping neural network to produce an intermediate latent code defined in an intermediate latent space. The intermediate latent code may be used as appearance vector that is processed by the synthesis neural network to generate an image. The appearance vector is a compressed encoding of data, such as video frames including a person's face, audio, and other data. Captured images may be converted into appearance vectors at a local device and transmitted to a remote device using much less bandwidth compared with transmitting the captured images. A synthesis neural network at the remote device reconstructs the images for display.
    Type: Grant
    Filed: October 13, 2020
    Date of Patent: February 14, 2023
    Assignee: NVIDIA Corporation
    Inventors: Tero Tapani Karras, Samuli Matias Laine, David Patrick Luebke, Jaakko T. Lehtinen, Miika Samuli Aittala, Timo Oskari Aila, Ming-Yu Liu, Arun Mohanray Mallya, Ting-Chun Wang
  • Patent number: 11582297
    Abstract: Methods, systems, and devices are provided herein for a mechanism to identify link down reasons. As described herein, a first port of a first peer device may be determined to have unexpectedly changed to a port down state. Subsequently, a topology file may be referenced to identify a second port of a second peer device with which the first peer device is intended to have a link if not for the first port being in a port down state. In some examples, port settings of the first port may be compared with port settings of the second port. If a port setting for the first port mismatches an associated port setting for the second port, an alert message may be transmitted to a network administrator indicating this mismatch as a possible reason for the first port being in the port down state.
    Type: Grant
    Filed: January 20, 2022
    Date of Patent: February 14, 2023
    Assignee: NVIDIA CORPORATION
    Inventor: Sudharsan Dhamal Gopalarathnam
  • Patent number: D978078
    Type: Grant
    Filed: July 24, 2019
    Date of Patent: February 14, 2023
    Assignee: NVIDIA Corporation
    Inventors: Hyoji Heidi Lim, Boris Landwehr, Pei-Lin Lo, Andrew Robert Bell, Gabriele Gorla, Timothy Lee, Yongju Kwak