Abstract: Convergence of threads executing common code sections is facilitated using instructions inserted at strategic locations in computer code sections. The inserted instructions enable the threads in a warp or other group to cooperate with a thread scheduler to promote thread convergence.

Abstract: PAM encoding techniques that leverage unused idle periods in channels between data transmissions to apply longer but more energy-efficient codes. To improve energy savings, multiple sparse encoding schemes may be utilized selectively to fit different sized gaps in the traffic. These approaches may provide energy reductions, for example with memory READ and WRITE traffic, when transferring 4-bit data using 3-symbol sequences.

Abstract: Techniques to improve the accuracy and speed for detection and remediation of difficult to test nodes in a circuit design netlist. The techniques utilize improved netlist representations, test point insertion, and trained neural networks.

Abstract: Various embodiments include a memory device that recovers from write errors and read errors more quickly relative to prior memory devices. Certain patterns of write data and read data may result on poor signal quality on the memory interface between memory controllers and memory devices. The disclosed memory device, synchronously with the memory controller, scrambles read data before transmitting the data to the memory controller and descrambles received from the memory controller. The scrambling and descrambling results in a different pattern on the memory interface even for the same read data or write data. Therefore, when a write operation or a read operation fails, and the operation is replayed, the pattern transmitted on the memory interface is different when the operation is replayed. As a result, the memory device more easily recovers from data patterns that cause poor signal quality on the memory interface.

Abstract: In various examples, a VPU and associated components may be optimized to improve VPU performance and throughput. For example, the VPU may include a min/max collector, automatic store predication functionality, a SIMD data path organization that allows for inter-lane sharing, a transposed load/store with stride parameter functionality, a load with permute and zero insertion functionality, hardware, logic, and memory layout functionality to allow for two point and two by two point lookups, and per memory bank load caching capabilities. In addition, decoupled accelerators may be used to offload VPU processing tasks to increase throughput and performance, and a hardware sequencer may be included in a DMA system to reduce programming complexity of the VPU and the DMA system. The DMA and VPU may execute a VPU configuration mode that allows the VPU and DMA to operate without a processing controller for performing dynamic region based data movement operations.

Abstract: In various examples, one or more components or regions of a processing unit—such as a processing core, and/or component thereof—may be tested for faults during deployment in the field. To perform testing while in deployment, the state of a component subject to test may be retrieved and/or stored during the test to maintain state integrity, the component may be clamped to communicatively isolate the component from other components of the processing unit, a test vector may be applied to the component, and the output of the component may be compared against an expected output to determine if any faults are present. The state of the component may be restored after testing, and the clamp removed, thereby returning the component to its operating state without a perceivable detriment to operation of the processing unit in deployment.

Abstract: In various examples, a test system is provided for executing built-in-self-test (BIST) on integrated circuits deployed in the field. The integrated circuits may include a first device and a second device, the first device having direct access to external memory, which stores test data, and the second device having indirect access to the external memory by way of the first device. In addition to providing a mechanism to permit the first device and the second device to run test concurrently, the hardware and software may reduce memory requirements and runtime associated with running the test sequences, thereby making real-time BIST possible in deployment. Furthermore, some embodiments permit a single external memory image to cater to different SKU configurations.

Abstract: A system includes a first device and a second device coupled to a link having one or more paths associated with transmitting a clock signal. The first device is to transmit a set of bits associated with a pattern via the one more paths. The set of bits are transmitted using a first clock signal having a first frequency less than a second frequency associated with data transmission operations. The second device is to receive the set of bits associated with the pattern, determine a number of pulses associated with the set of bits over a first period, and determine the number of pulses, associated with the set of bits, satisfies a predetermined condition relating to the number of pulses for the first period. The second device is to initiate a training of the link in response to determining the number of pulses satisfies the predetermined condition.

Abstract: Systems and methods for detecting blockages in images are described. An example method may include receiving a plurality of images captured by a camera installed on an apparatus. The method may include identifying one or more candidate blocked regions in the plurality of images. Each of the candidate blocked regions may contain image data caused by blockages in the camera's field-of-view. The method may further include assigning scores to the one or more candidate blocked regions based on relationships among the one or more candidate blocked regions in the plurality of images. In response to a determination that one of the scores is above a predetermined blockage threshold, the method may include generating an alarm signal for the apparatus.

Abstract: In various examples, a system includes a memory operating within a first risk level and circuitry operating within a second risk level that indicates more risk than the first risk level. The circuitry reads and/or writes data to a first memory address within the memory, and reads and/or writes an error detection code to a second memory address within the memory.

Abstract: In various examples, a VPU and associated components may be optimized to improve VPU performance and throughput. For example, the VPU may include a min/max collector, automatic store predication functionality, a SIMD data path organization that allows for inter-lane sharing, a transposed load/store with stride parameter functionality, a load with permute and zero insertion functionality, hardware, logic, and memory layout functionality to allow for two point and two by two point lookups, and per memory bank load caching capabilities. In addition, decoupled accelerators may be used to offload VPU processing tasks to increase throughput and performance, and a hardware sequencer may be included in a DMA system to reduce programming complexity of the VPU and the DMA system. The DMA and VPU may execute a VPU configuration mode that allows the VPU and DMA to operate without a processing controller for performing dynamic region based data movement operations.

Abstract: Approaches are presented for training and using scene graph generators for transfer learning. A scene graph generation technique can decompose a domain gap into individual types of discrepancies, such as may relate to appearance, label, and prediction discrepancies. These discrepancies can be reduced, at least in part, by aligning the corresponding latent and output distributions using one or more gradient reversal layers (GRLs). Label discrepancies can be addressed using self-pseudo-statistics collected from target data. Pseudo statistic-based self-learning and adversarial techniques can be used to manage these discrepancies without the need for costly supervision from a real-world dataset.

Abstract: In various examples, recordings of gameplay sessions are enhanced by the application of special effects to relatively high(er) and/or low(er) interest durations of the gameplay sessions. Durations of relatively high(er) or low(er) predicted interest in a gameplay session are identified, for instance, based upon level of activity engaged in by a gamer during a particular gameplay session duration. Once identified, different variations of video characteristic(s) are applied to at least a portion of the identified durations for implementation during playback. The recordings may be generated and/or played back in real-time with a live gameplay session, or after completion of the gameplay session. Further, video data of the recordings themselves may be modified to include the special effects and/or indications of the durations and/or variations may be included in metadata and used for playback.

Abstract: In various examples, systems and methods of the present disclosure combine open and closed dialog systems into an intelligent dialog management system. A text query may be processed by a natural language understanding model trained to associate the text query with a domain tag, intent classification, and/or input slots. Using the domain tag, the natural language understanding model may identify information in the text query corresponding to input slots needed for answering the text query. The text query and related information may then be passed to a dialog manager to direct the text query to the proper domain dialog system. Responses retrieved from the domain dialog system may be provided to the user via text output and/or via a text to speech component of the dialog management system.

Abstract: The autonomous vehicle generates an overlapped image by overlaying HD map data over sensor data and rendering the overlaid images. The visualization process is repeated as the vehicle drives along the route. The visualization may be displayed on a screen within the vehicle or at a remote device. The system performs reverse rendering of a scene based on map data from a selected point. For each line of sight originating at the selected point, the system identifies the farthest object in the map data. Accordingly, the system eliminates objects obstructing the view of the farthest objects in the HD map as viewed from the selected point. The system further allows filtering of objects using filtering criteria based on semantic labels. The system generates a view from the selected point such that 3D objects matching the filtering criteria are eliminated from the view.

Abstract: A system includes a first device and a second device coupled to a link. The first device is to transmit one or more request frames for synchronization of a data layer, each request frame including a quantity of bits and an error code. The second device is to receive a first set of bits corresponding to the quantity of bits in each request frame. The second device is to perform an error decode operation on the first set of bits using a first portion of the first set of bits and determine the first set of bits correspond to a frame boundary of the one more request frames responsive to a success of the error decode operation. The second device is to transmit an acknowledgement of the synchronization of the data layer based on determining the first set of bits corresponds to the frame boundary.

Abstract: The disclosure is directed to a process that can predict and prevent an audio artifact from occurring. The process can monitor the systems, processes, and execution threads on a larger system/device, such as a mobile or in-vehicle device. Using a learning algorithm, such as deep neural network (DNN), the information collected can generate a prediction of whether an audio artifact is likely to occur. The process can use a second learning algorithm, which also can be a DNN, to generate recommended system adjustments that can attempt to prevent the audio glitch from occurring. The recommendations can be for various systems and components on the device, such as changing the processing system frequency, the memory frequency, and the audio buffer size. After the audio artifact has been prevented, the system adjustments can be reversed fully or in steps to return the system to its state prior to the system adjustments.

Abstract: Apparatuses, systems, and techniques to perform a fast Fourier transform operation. In at least one embodiment, a fast Fourier transform operation is performed based on one or more parameters, wherein the one or more parameters indicate information about one or more operands of the fast Fourier transform.

Abstract: Apparatuses, systems, and techniques to train and apply a first machine learning model to identify a plurality of regions of interest within an input image, and to train and apply a plurality of second machine learning models to identify one or more objects within each region of interest identified by the first machine learning model.

Abstract: For mechanical keyboards or other input devices with individual mechanical key buttons, and particularly for compact keyboards used for laptops and other such devices, the size of the up and down arrow keys is usually half the size of most other keys on the keyboard. For example, each letter key on a physical keyboard is typically double the size of each of the up and down arrow keys on that same keyboard. Due to the smaller physical size of the up and down arrow keys, a modified mechanical configuration is used which results in a variation in the tactile feel of the various buttons of the keyboard for a user. The present disclosure discloses a capacitive touch enabled key with a corresponding tactile button to allow the key to represent multiple different inputs while also maintaining a same tactile response as other single input keys of the input device.