Abstract: One embodiment of the present invention includes techniques for processing a multi-resolution hierarchy, where an application configures a ROP unit to render all the levels included in the multi-resolution hierarchy to a single composite render target. The ROP unit renders memory pages to the composite render target in pitch order. In contrast, the texture unit accesses the composite render target with memory pages in pitch order for each level of the hierarchy. The application configures the MMU to ensure that the composite render target is correctly interpreted by the texture unit. Notably, the MMU translates ROP unit virtual addresses and texture unit virtual addresses using different mapping strategies to the same physical address space. One advantage of the disclosed embodiments is that rendering to the multi-resolution hierarchy does not require the CPU to execute the state parameter changes that are associated with rendering the different hierarchical levels using prior-art techniques.

Abstract: An electronic computing system for dynamically controlling user interface device settings for an electronic game playable by multiple players over a computer network.

Abstract: Embodiments of the present invention provide a novel solution to generate multiple linked device code portions within a final executable file. Embodiments of the present invention are operable to extract device code from their respective host object filesets and then link them together to form multiple linked device code portions. Also, using the identification process described by embodiments of the present invention, device code embedded within host objects may also be uniquely identified and linked in accordance with the protocols of conventional programming languages. Furthermore, these multiple linked device code portions may be then converted into distinct executable forms of code that may be encapsulated within a single executable file.

Abstract: A method, system and computer program product embodied on a computer-readable medium are provided for managing the execution of out-of-order instructions. The method includes the steps of receiving a plurality of instructions and identifying a subset of instructions in the plurality of instructions to be executed out-of-order.

Abstract: Embodiments of the present invention are directed to techniques for improving the efficiency of shadow mapping by using highly optimized hardware-accelerated rasterizers. Embodiments of the present invention use a shader (such as a fragment or compute shader) to construct advanced shadow maps which store a list of polygons that intersect each pixel, and synchronizing read/write operations (e.g., with atomics) to ensure consistency of the texture accesses when managing the per-texel triangle lists during creation. By using these hardware-accelerated and optimized techniques, high quality hard shadows can be produced during real-time rendering, as performed in graphics processing engines, for example. Moreover, this technique can be synchronized with other pre-fragment features that are becoming increasingly prevalent and efficient in the latest processing architectures.

Abstract: Embodiments of the present invention are directed to methods and systems for performing automatic noise reduction in video. According to one aspect of the invention, a video noise-reducing system is provided consisting of a noise estimator, a motion classifier, two stages of filters, each including a spatial and temporal filter, and a combiner. The system adapts to noise level and to scene content to find at each location in the image a balance of noise reduction and detail preservation. Temporal Infinite Impulse Response (IIR) filtering provides a high level of detail-preserving noise reduction where motion allows, while non linear spatial filtering provides edge-preserving noise reduction in areas where the temporal filter would introduce motion artifacts. A spatial-temporal combiner provides smooth transition and balance between the two filtering modes; this block also enables use of external cues to produce a visually pleasing output based on ambient conditions.

Abstract: In one embodiment of the present invention, a convolution engine configures a parallel processing pipeline to perform multi-convolution operations. More specifically, the convolution engine configures the parallel processing pipeline to independently generate and process individual image tiles. In operation, for each image tile, the pipeline calculates source locations included in an input image batch based on one or more start addresses and one or more offsets. Subsequently, the pipeline copies data from the source locations to the image tile. The pipeline then performs matrix multiplication operations between the image tile and a filter tile to generate a contribution of the image tile to an output matrix. To optimize the amount of memory used, the pipeline creates each image tile in shared memory as needed. Further, to optimize the throughput of the matrix multiplication operations, the values of the offsets are precomputed by a convolution preprocessor.

Abstract: A system for cooperative game control. In one embodiment, the system includes: (1) a cloud game engine for executing game code configured to create a game, generate a video stream corresponding to a particular player and accept a response stream from the particular player to allow the particular player to play the game and (2) a cooperative play engine associated with the cloud game engine for communication therewith and configured to multicast the video stream from the cloud game engine to the particular player and at least one other player, combine separate response streams from the particular player and the at least one other player into a joint response stream and provide the joint response stream to the cloud game engine.

Abstract: One embodiment of the present invention sets forth a technique that provides an efficient way to retrieve operands from a register file. Specifically, the instruction dispatch unit receives one or more instructions, each of which includes one or more operands. Collectively, the operands are organized into one or more operand groups from which a shaped access may be formed. The operands are retrieved from the register file and stored in a collector. Once all operands are read and collected in the collector, the instruction dispatch unit transmits the instructions and corresponding operands to functional units within the streaming multiprocessor for execution. One advantage of the present invention is that multiple operands are retrieved from the register file in a single register access operation without resource conflict. Performance in retrieving operands from the register file is improved by forming shaped accesses that efficiently retrieve operands exhibiting recognized memory access patterns.

Abstract: A subsystem configured to upsample a video data stream encoded in YCrCb format 4:2:0 (also termed YUV 4:2:0) performs an algorithm upon a two-by-two group of subsampled pixels. The subsystem computes an inside probability that the chrominance of a target pixel is a close match to the chrominance inside the group of four pixels. The subsystem further computes three weighting factors relating the chrominance of the target pixel to each of three adjacent pixels in an upsampled four-by-four pixel group. The subsystem then computes an outside estimate of the chrominance based on the weighting factors. Finally, the subsystem computes the chrominance of the target pixel based on the inside probability, the outside estimate, and the subsampled chrominance. The subsystem performs the algorithm upon all two-by-two groups of four pixels within a subsampled YUV 4:2:0 video data stream and generates an upsampled YUV 4:4:4 video data stream.

Abstract: A subsystem configured to write data to a static random access memory cell employs a single N-channel MOS device connected to ground in each leg of the bi-stable memory cell to overdrive the stored data. The subsystem implements the dual control required to effect matrix operation of the SRAM cell in the gate circuit of the single N-channel MOS device in the drive path. Specifically, the column select signal controls a semiconductor junction that interrupts the data connection to the gate. In this manner, the column select control is removed from the drive path, thus increasing drive strength. Further, a second semiconductor junction connects the gate of the single NMOS device in the drive path when the gate signal is interrupted.

Abstract: A graphics processor and a method of scaling user interface (UI) elements for smaller displays. One embodiment of the graphics processor includes: (1) a scene renderer configured to render a scene from scene data generated by a graphics application, (2) a user interface (UI) renderer configured to render a UI from UI data generated by the graphics application, (3) a UI scaler configured to scale the UI based on properties of a remote display, and (4) a compositor operable to combine the scene and the UI into a composite image.

Abstract: A strain based dynamic technique, for rendering special effects, includes simulation as a function of a Green-St. Venant strain tensor constraint. The behavior of a soft body may be controlled independent of a mesh structure by assigning different stiffness values to each constraint of the Green-St. Venant strain tensor.

Abstract: One embodiment of the present invention sets forth an integrated circuit that includes multiple input/output (I/O) pad groups. Each I/O pad group includes an on-chip star network, multiple I/O pads, multiple test multiplexers, a digital-to-analog converter (DAC), and a wide-range comparator. Each test multiplexer is configured to couple a different I/O pad to the on-chip star network. The DAC is configured to supply at least one of a source current, a sink current, and a first reference voltage to the on-chip star network. The wide-range comparator is configured to compare a voltage present on a first I/O pad included in the plurality of I/O pads with a second reference voltage. Advantageously, IO leakage and DC parametric testing may be performed on integrated circuits with high I/O pad counts using an ATE system with a significantly lower quantity of ATE test channels relative to prior approaches.

Abstract: A system and method for processing source code for compilation. The method includes accessing a portion of host source code and determining whether the portion of the host source code comprises a device lambda expression. The method further includes in response to the portion of host code comprising the device lambda expression, determining a unique placeholder type instantiation based on the device lambda expression and modifying the device lambda expression based on the unique placeholder type instantiation to produce modified host source code. The method further includes sending the modified host source code to a host compiler.

Abstract: An apparatus, computer readable medium, and method are disclosed for performing an intersection query between a query beam and a target bounding volume. The target bounding volume may comprise an axis-aligned bounding box (AABB) associated with a bounding volume hierarchy (BVH) tree. An intersection query comprising beam information associated with the query beam and slab boundary information for a first dimension of a target bounding volume is received. Intersection parameter values are calculated for the first dimension based on the beam information and the slab boundary information and a slab intersection case is determined for the first dimension based on the beam information. A parametric variable range for the first dimension is assigned based on the slab intersection case and the intersection parameter values and it is determined whether the query beam intersects the target bounding volume based on at least the parametric variable range for the first dimension.

Abstract: A video encoder, a method of encoding a frame of video data, and a three-dimensional modeling system producing an encoded video stream are disclosed herein. In one embodiment, the method includes: (1) receiving from an application a frame of video data to be encoded, (2) determining a gamer's attention area for the frame of video data and (3) changing an encoding of the frame of video data by allocating bits for the frame based upon the gamer's attention area.

Abstract: An issue control unit is configured to control the rate at which an instruction issue unit issues instructions to an execution pipeline in order to avoid spikes in power drawn by that execution pipeline. The issue control unit maintains a history buffer that reflects, for N previous cycles, the number of instructions issued during each of those N cycles. If the total number of instructions issued during the N previous cycles exceeds a threshold value, then the issue control unit throttles the instruction issue unit from issuing instructions during a subsequent cycle. In addition, the issue control unit increases the threshold value in proportion to the number of previously issued instructions and based on a variety of configurable parameters. Accordingly, the issue control unit maintains granular control over the rate with which the instruction issue unit “ramps up” to a maximum instruction issue rate.

Abstract: A processing system comprising a microprocessor core and a translator. Within the microprocessor core is arranged a hardware decoder configured to selectively decode instructions for execution in the microprocessor core, and, a logic structure configured to track usage of the hardware decoder. The translator is operatively coupled to the logic structure and configured to selectively translate the instructions for execution in the microprocessor core, based on the usage of the hardware decoder as determined by the logic structure.

Abstract: A system and method are provided for a 3D modeling system with which an encoded video stream is produced. The system includes a content engine, an encoder, and a fixed function engine. The fixed function engine receives content information from the content engine. The fixed function engine produces encoder information from the content information. The encoder uses the encoder information to produce an encoded video stream having at least one of a higher quality and a lower bandwidth than a video stream encoded without the encoder information.