Abstract: The disclosure is directed to a method to generate a generated stereoscopic video image stream of a zenith or nadir view perspective of a scene utilizing a blending of stereoscopic and monoscopic view perspectives. In another aspect, a system is disclosed for generating a zenith or nadir view perspective utilizing a relative user view orientation. In another aspect, an apparatus is disclosed capable to generate a zenith or nadir view perspective utilizing a detected user view orientation, and display a generated stereoscopic video image stream of the view perspective.
Abstract: One embodiment of the present invention includes a microcontroller coupled to a memory management unit (MMU). The MMU is coupled to a page table included in a physical memory, and the microcontroller is configured to perform one or more virtual memory operations associated with the physical memory and the page table. In operation, the microcontroller receives a page fault generated by the MMU in response to an invalid memory access via a virtual memory address. To remedy such a page fault, the microcontroller performs actions to map the virtual memory address to an appropriate location in the physical memory. By contrast, in prior-art systems, a fault handler would typically remedy the page fault. Advantageously, because the microcontroller executes these tasks locally with respect to the MMU and the physical memory, latency associated with remedying page faults may be decreased. Consequently, overall system performance may be increased.
Type:
Grant
Filed:
August 27, 2013
Date of Patent:
September 10, 2019
Assignee:
NVIDIA CORPORATION
Inventors:
Cameron Buschardt, Jerome F. Duluk, Jr., John Mashey, Mark Hairgrove, James Leroy Deming, Brian Fahs
Abstract: Embodiments of the present invention provide a method for simulating deformable solids undergoing large plastic deformation and topological changes using shape matching. Positional information for particles and orientation information from clusters is used to simulate deformable solids represented by particles. Each visual vertex stores references to particles that influence the vertex, and stores the local position of the particles. A two-step method interpolates orientation from clusters to particles, and uses the orientation and position of particles to skin the visual mesh vertices. This results in a fast method that can reproduce rotation and does not require the visual mesh vertex to be located within a convex hull of particles.
Type:
Grant
Filed:
July 11, 2017
Date of Patent:
September 10, 2019
Assignee:
Nvidia Corporation
Inventors:
Nuttapong Chentanez, Matthias Mueller-Fischer, Miles Macklin
Abstract: A virtual reality (VR) audio rendering system and method using pre-computed impulse responses (IRs) to generate audio frames in a VR setting for rendering. Based on a current position of a user or a VR object, a set of possible motions are predicted and a set of IRs are pre-computed by using a Geometric Acoustic (GA) model of a virtual scene. Once a position change is actually detected, one of the pre-computed IRs is selected and convolved with a set of audio frames to generate modified audio frames for rendering. As the modified audio frames are generated by using pre-computed IR without requiring intensive ray tracing computations, the audio latency can be significantly reduced.
Abstract: In one embodiment of the present invention a cache unit organizes data stored in an attached memory to optimize accesses to compressed data. In operation, the cache unit introduces a layer of indirection between a physical address associated with a memory access request and groups of blocks in the attached memory. The layer of indirection—virtual tiles—enables the cache unit to selectively store compressed data that would conventionally be stored in separate physical tiles included in a group of blocks in a single physical tile. Because the cache unit stores compressed data associated with multiple physical tiles in a single physical tile and, more specifically, in adjacent locations within the single physical tile, the cache unit coalesces the compressed data into contiguous blocks. Subsequently, upon performing a read operation, the cache unit may retrieve the compressed data conventionally associated with separate physical tiles in a single read operation.
Type:
Grant
Filed:
October 28, 2015
Date of Patent:
September 3, 2019
Assignee:
NVIDIA CORPORATION
Inventors:
Praveen Krishnamurthy, Peter B. Holmquist, Wishwesh Gandhi, Timothy Purcell, Karan Mehra, Lacky Shah
Abstract: A display method and system are disclosed for virtual/augmented reality. The method includes the steps of generating an image by a projection engine and projecting light rays defining the image onto a diffuser holographic optical element (DHOE) located between an observer and a concave mirror element, where a concave surface of the concave mirror element faces the observer. The light rays are projected onto the DHOE at a reference angle that causes the light rays to be diffused to the concave surface of the concave mirror element and the diffused light rays are reflected back to the observer such that the observer perceives a virtual image that appears to the observer at a position behind the concave mirror element and further from the observer than the concave mirror element.
Type:
Grant
Filed:
November 9, 2018
Date of Patent:
September 3, 2019
Assignee:
NVIDIA Corporation
Inventors:
Jonghyun Kim, Kaan Aksit, Ward Lopes, David Patrick Luebke
Abstract: A method for rendering graphics frames allocates rendering work to multiple graphics processing units (GPUs) that are configured to allow access to pages of data stored in locally attached memory of a peer GPU. The method includes the steps of generating, by a first GPU coupled to a first memory circuit, one or more first memory access requests to render a first primitive for a first frame, where at least one of the first memory access requests targets a first page of data that physically resides within a second memory circuit coupled to a second GPU. The first GPU requests the first page of data through a first data link coupling the first GPU to the second GPU and a register circuit within the first GPU accumulates an access request count for the first page of data. The first GPU notifies a driver that the access request count has reached a specified threshold.
Type:
Grant
Filed:
December 28, 2017
Date of Patent:
September 3, 2019
Assignee:
NVIDIA Corporation
Inventors:
Rouslan L. Dimitrov, Kirill A. Dmitriev, Andrei Khodakovsky, Tzyywei Hwang, Wishwesh Anil Gandhi, Lacky Vasant Shah
Abstract: A system comprising a PAM-4 transmitter coupled data lanes includes a least significant bit section and a most significant bit section for the symbols generated on each lane. A controller to determine a state of the PAM-4 transmitter and selectively inverts a polarity of the symbol bits on the lanes based on the state.
Abstract: A method, computer readable medium, and system are disclosed for classifying video image data. The method includes the steps of processing training video image data by at least a first layer of a convolutional neural network (CNN) to extract a first set of feature maps and generate classification output data for the training video image data. Spatial classification accuracy data is computed based on the classification output data and target classification output data and spatial discrimination factors for the first layer are computed based on the spatial classification accuracies and the first set of feature maps.
Type:
Grant
Filed:
July 26, 2017
Date of Patent:
September 3, 2019
Assignee:
NVIDIA Corporation
Inventors:
Xiaodong Yang, Pavlo Molchanov, Jan Kautz
Abstract: A method, computer readable medium, and system are disclosed for adjusting an angular sampling rate during rendering. The method includes the steps of determining a location of a gaze within a displayed scene, and adjusting, during a rendering of the scene, an angular sampling rate used to render at least a portion of the scene, based on the location of the gaze within the displayed scene.
Type:
Grant
Filed:
January 25, 2018
Date of Patent:
August 27, 2019
Assignee:
NVIDIA Corporation
Inventors:
Qi Sun, Fu-Chung Huang, Joohwan Kim, David Patrick Luebke
Abstract: In embodiments of the invention, a method may include displaying an array of slits using a first light-attenuating spatial light modulator, displaying a pre-filtered image using a second light-attenuating SLM by attenuating rays of light originating from a surrounding environment to synthesis a near-eye light field, where the rays of light pass through the first and second light-attenuating SLMs, and selectively blocking the rays of light originating from the surrounding environment using the array of slits to generate a virtual image in said near-eye light field.
Type:
Grant
Filed:
March 1, 2018
Date of Patent:
August 27, 2019
Assignee:
NVIDIA Corporation
Inventors:
David Luebke, Douglas Patrick Lanman, Thomas Francis Fox, Gerrit Slavenburg
Abstract: One embodiment of the present invention includes a boot read only memory (ROM) with an embedded, private key provision key (KPK) set that enables secure provisioning of chips. As part of taping-out a chip, the chip provider establishes the KPK set and provides the boot ROM exclusive access to the KPK. For each Original Equipment Manufacturer (OEM), the chip provider assigns and discloses an OEM-specific KPK that is included in the KPK set at a particular KPK index. Upon receiving a secured provisioning image and the associated KPK index, the boot ROM accesses the KPK set to reconstruct the KPK and then decrypts and executes the secured provisioning image. Advantageously, this enables the manufacturing factory to provision the chip without the security risks attributable to conventional provisioning approaches that require disclosing security keys to the manufacturing factory.
Abstract: One embodiment provides a method for reducing leakage current in device logic having an operational supply-voltage threshold, a nonzero data-retention supply voltage threshold, and two or more on-die transistor switches to switchably connect a voltage source to the device logic. After the logic enters an idle period, one or more of the switches are opened to lower a supply voltage of the logic below the operational supply-voltage threshold but above the data-retention supply-voltage threshold. When the logic exits the idle period, one or more of the switches are closed to raise the supply voltage of the logic above the operational supply-voltage threshold.
Abstract: A method, computer readable medium, and system are disclosed for dynamic facial analysis. The method includes the steps of receiving video data representing a sequence of image frames including at least one head and extracting, by a neural network, spatial features comprising pitch, yaw, and roll angles of the at least one head from the video data. The method also includes the step of processing, by a recurrent neural network, the spatial features for two or more image frames in the sequence of image frames to produce head pose estimates for the at least one head.
Type:
Grant
Filed:
December 8, 2017
Date of Patent:
August 6, 2019
Assignee:
NVIDIA Corporation
Inventors:
Jinwei Gu, Xiaodong Yang, Shalini De Mello, Jan Kautz
Abstract: A gaming cloud gaming system and a method of initiating a gaming session. One embodiment of the gaming cloud gaming system includes a computing system having: (1) an entry point operable to receive a game session request and generate instructions for establishing a connection between a client and a game server, and (2) a dynamically configurable reverse proxy operable to proxy for the game server and configured to employ the instructions to create a route to a randomly selected port on the game server through which the connection is makeable.
Abstract: A technique for managing a parallel cache hierarchy that includes receiving an instruction from a scheduler unit, where the instruction comprises a load instruction or a store instruction; determining that the instruction includes a cache operations modifier that identifies a policy for caching data associated with the instruction at one or more levels of the parallel cache hierarchy; and executing the instruction and caching the data associated with the instruction based on the cache operations modifier.
Type:
Grant
Filed:
May 1, 2017
Date of Patent:
July 30, 2019
Assignee:
NVIDIA CORPORATION
Inventors:
John R. Nickolls, Brett W. Coon, Michael C. Shebanow
Abstract: A magnetic power supply coupling system is disclosed. An integrated circuit module includes an integrated circuit die and a secondary winding that is configured to generate an induced, alternating current based on a magnetic flux. A primary winding is external to the integrated circuit module, proximate to the integrated circuit module, and coupled to a main power supply corresponding to an alternating current that generates the magnetic flux. The induced, alternating current is converted into a direct current at a voltage level to supply power to the integrated circuit die.
Type:
Grant
Filed:
July 31, 2015
Date of Patent:
July 23, 2019
Assignee:
NVIDIA Corporation
Inventors:
William J. Dally, Thomas Hastings Greer, III, Sudhir Shrikantha Kudva
Abstract: A mechanism for predicated execution of instructions within a parallel processor executing multiple threads or data lanes is disclosed. Each thread or data lane executing within the parallel processor is associated with a predicate register that stores a set of 1-bit predicates. Each of these predicates can be set using different types of predicate-setting instructions, where each predicate setting instruction specifies one or more source operands, at least one operation to be performed on the source operands, and one or more destination predicates for storing the result of the operation. An instruction can be guarded by a predicate that may influence whether the instruction is executed for a particular thread or data lane or how the instruction is executed for a particular thread or data lane.
Type:
Grant
Filed:
September 27, 2010
Date of Patent:
July 23, 2019
Assignee:
NVIDIA CORPORATION
Inventors:
Richard Craig Johnson, John R. Nickolls, Robert Steven Glanville
Abstract: A method, computer readable medium, and system are disclosed for image processing to reduce aliasing using a temporal anti-aliasing algorithm modified to implement variance clipping. The method includes the step of generating a current frame of image data in a memory. Then, each pixel in the current frame of image data is processed by: sampling a resolved pixel color for a corresponding pixel in a previous frame of image data stored in the memory, adjusting the resolved pixel color based on a statistical distribution of color values for a plurality of samples in the neighborhood of the pixel in the current frame of image data to generate an adjusted pixel color, and blending a color value for the pixel in the current frame of image data with the adjusted pixel color to generate a resolved pixel color for the pixel in the current frame of image data.
Type:
Grant
Filed:
August 1, 2018
Date of Patent:
July 23, 2019
Assignee:
NVIDIA Corporation
Inventors:
Marco Salvi, Anjul Patney, Aaron Eliot Lefohn