Patents Assigned to NVidia
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Patent number: 10097203Abstract: A CRC generator, a method for computing a CRC of a data packet, and an electronic system, such as a circuit board, are disclosed herein. In one embodiment the method is for computing the CRC of a data packet to be transmitted on a serial communications link having multiple lanes. In one embodiment, the CRC generator includes: (1) a CRC calculator configured to define a CRC calculation of a data packet in sequential order and perform parallelized computations, according to the sequential order and the multiple lanes, to generate sub-CRC values and (2) combination circuitry configured to combine the sub-CRC values to provide the CRC value for the packet.Type: GrantFiled: November 12, 2015Date of Patent: October 9, 2018Assignee: Nvidia CorporationInventors: Eric Tyson, Stephen D. Glaser, Mike Osborn, Mark Hummel
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Patent number: 10091251Abstract: In one aspect there is provided a host device having: a modem interface arranged to transmit transmission units between the host device and a modem; a communication function configured to generate primitives to establish a communication event between the host device and a remote device; a client agent connected to receive control primitives from the communication function and operable to convert the control primitives to data transmission units; a host routing interface operable to route data transmission units from the client agent according to a predetermined route option which is set based on whether a communication event control function for processing the data transmission units is located on the host device or the modem.Type: GrantFiled: April 4, 2013Date of Patent: October 2, 2018Assignee: Nvidia CorporationInventors: Thomas Fleury, Flavien Delorme
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Patent number: 10089707Abstract: A server and methods for performing an ultra-high resolution pan-scan on displays connected across multiple client GPUs are provided. In one embodiment, one of the methods includes: 1) rendering a surface that exceeds resolutions of displays connected to multiple client GPUs; 2) receiving viewport coordinates of one of the displays that is connected to one of the multiple client GPUs; 3) encoding only a portion of the surface that corresponds to the viewport coordinates; 4) sending the portion to the one of the multiple client GPUs.Type: GrantFiled: February 15, 2016Date of Patent: October 2, 2018Assignee: Nvidia CorporationInventors: Praful Jotshi, Uday Dhoke, Aamod Gokhale
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Patent number: 10083514Abstract: One embodiment of the present invention includes techniques for rasterizing primitives that include edges shared between paths. For each edge, a rasterizer unit selects and applies a sample rule from multiple sample rules. If the edge is shared, then the selected sample rule causes each group of coverage samples associated with a single color sample to be considered as either fully inside or fully outside the edge. Consequently, conflation artifacts caused when the number of coverage samples per pixel exceeds the number of color samples per pixel may be reduced. In prior-art techniques, reducing such conflation artifacts typically involves increasing the number of color samples per pixel to equal the number of coverage samples per pixel. Advantageously, the disclosed techniques enable rendering using algorithms that reduce the ratio of color to coverage samples, thereby decreasing memory consumption and memory bandwidth use, without causing conflation artifacts associated with shared edges.Type: GrantFiled: October 10, 2016Date of Patent: September 25, 2018Assignee: NVIDIA CORPORATIONInventors: Mark J. Kilgard, Jeffrey A. Bolz
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Patent number: 10083036Abstract: One embodiment of the present invention sets forth a technique for managing graphics processing resources in a tile-based architecture. The technique includes storing a release packet associated with a graphics processing resource in a buffer and initiating a replay of graphics primitives stored in the buffer and associated with the graphics processing resource. The technique further includes, for each tile included in a plurality of tiles and processed during the replay, reading the release packet and determining whether the tile is a last tile processed during the replay. The technique further includes determining not to transmit the release packet to a screen-space pipeline and continuing to read graphics data stored in the buffer if the tile is not the last tile to be processed during the replay, or transmitting the release packet to the screen-space pipeline if the tile is the last tile to be processed during the replay.Type: GrantFiled: October 3, 2013Date of Patent: September 25, 2018Assignee: NVIDIA CORPORATIONInventors: Ziyad S. Hakura, Cynthia Ann Edgeworth Allison, Dale L. Kirkland, Andrei Khodakovsky, Jeffrey A. Bolz
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Patent number: 10083932Abstract: A method of forming a package on package, semiconductor package arrangement is described. In one aspect, solder bumps on a lower surface of a first grid array package substrate are fused to corresponding unencapsulated solder bumps on an upper surface of a second grid array package substrate. The fused solder bumps form solder joints that electrically connect the first and second packages. The height of the resulting solder joints is greater than a height of a die that is flip chip mounted to the second substrate such that the first substrate does not contact any portion of the second package and an air gap is formed that separates the second die from the first package. Corresponding PoP packages structures are also described.Type: GrantFiled: January 17, 2014Date of Patent: September 25, 2018Assignee: NVIDIA CorporationInventor: Ernesto A. Opiniano
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Patent number: 10080161Abstract: A method, a transmitter and a computer program product for processing data units at the transmitter are disclosed. In one embodiment, data units are transmitted to a receiver according to a protocol and with respective sequence numbers. The protocol indicates that the receiver is to use a reordering window to determine whether a data unit which is newly received from the transmitter is a new or repeated data unit the data stream by comparing the sequence numbers of the newly received data unit and a previously received data unit. A status report is received and based thereon, the sequence number of a next data unit to be transmitted in a new cell following a handover is selectively adjusted such that the next data unit will be determined to be a new data unit. The next data unit is transmitted with the adjusted sequence number to the receiver.Type: GrantFiled: December 17, 2012Date of Patent: September 18, 2018Assignee: Nvidia CorporationInventor: Alexander May
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Patent number: 10078911Abstract: A system, method, and computer program product are provided for executing processes involving at least one primitive in a graphics processor, utilizing a data structure. In operation, a data structure is associated with at least one primitive. Additionally, a plurality of processes involving the at least one primitive are executed in a graphics processor, utilizing the data structure. Moreover, the plurality of processes include at least one of selecting at least one surface or portion thereof to which to render, or selecting at least one of a plurality of viewports.Type: GrantFiled: March 15, 2013Date of Patent: September 18, 2018Assignee: NVIDIA CorporationInventors: Ziyad Sami Hakura, Yury Uralsky, Tyson Bergland, Eric Brian Lum, Jerome F. Duluk, Henry Packard Moreton
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Patent number: 10079746Abstract: A system and method for testing a data channel are provided. In one embodiment, the method includes: (1) transmitting groups of increasing numbers of probing packets of a uniform load over successive time periods over the data channel and (2) determining a bandwidth of the data channel based on receive times and loads of at least some of successfully received ones of the groups.Type: GrantFiled: September 11, 2015Date of Patent: September 18, 2018Assignee: Nvidia CorporationInventors: Reza Marandian Hagh, Xuezhou Ma, Sudhakar Aluri, Thomas Meier
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Patent number: 10074212Abstract: A method and renderer for a progressive computation of a light transport simulation are provided. The method includes the steps of employing a low discrepancy sequence of samples; and scrambling an index of the low discrepancy sequence independently per region using a hash value based on coordinates of a respective region, wherein for each set of a power-of-two number of the samples, the scrambling is a permutation.Type: GrantFiled: July 28, 2016Date of Patent: September 11, 2018Assignee: Nvidia CorporationInventors: Carsten Waechter, Nikolaus Binder
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Patent number: 10074411Abstract: A memory driver, a method of driving a command bus for a synchronous dual data rate (sDDR) memory and a memory controller for controlling dynamic random-access memory (DRAM). In one embodiment, the memory driver includes: (1) pull-up and pull-down transistors couplable to a command bus of a memory controller and operable in 1N and 2N timing modes and (2) gear down offset circuitry coupled to the pull-up transistor and operable to offset the command bus when transitioning out of the 1N timing mode and increase an extent and duration of 1-0-1 transitions on the command bus.Type: GrantFiled: January 24, 2014Date of Patent: September 11, 2018Assignee: Nvidia CorporationInventors: Daehyun Chung, Sunil Sudhakaran
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Patent number: 10068549Abstract: A method, computer program product, and system for cursor handling in a variable refresh rate environment are disclosed. The method includes the steps of receiving a first image, combining a cursor at a first position with the first image to produce a first combined image, and displaying the combined image on a variable refresh rate display device. The method also includes the steps of determining that a refresh timeout associated with the variable refresh rate display device has occurred, and then, after determining that a second image has not been generated, combining the cursor at a second position with the first image to produce a second combined image for display. The logic for implementing the method may be included in a graphics processing unit or within the variable refresh rate display device itself.Type: GrantFiled: September 16, 2015Date of Patent: September 4, 2018Assignee: NVIDIA CORPORATIONInventors: Tom Verbeure, Timothy John Bornemisza
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Patent number: 10067768Abstract: A method, system, and computer program product for executing divergent threads using a convergence barrier are disclosed. A first instruction in a program is executed by a plurality of threads, where the first instruction, when executed by a particular thread, indicates to a scheduler unit that the thread participates in a convergence barrier. A first path through the program is executed by a first divergent portion of the participating threads and a second path through the program is executed by a second divergent portion of the participating threads. The first divergent portion of the participating threads executes a second instruction in the program and transitions to a blocked state at the convergence barrier. The scheduler unit determines that all of the participating threads are synchronized at the convergence barrier and the convergence barrier is cleared.Type: GrantFiled: July 13, 2015Date of Patent: September 4, 2018Assignee: NVIDIA CORPORATIONInventors: Gregory Frederick Diamos, Richard Craig Johnson, Vinod Grover, Olivier Giroux, Jack H. Choquette, Michael Alan Fetterman, Ajay S. Tirumala, Peter Nelson, Ronny Meir Krashinsky
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Patent number: 10068366Abstract: A method, computer readable medium, and system are disclosed for generating multi-view image data. The method includes the steps of processing primitive data of a model to generate processed primitive data that includes multiple position vectors for each vertex in the primitive data, the number of position vectors associated with each vertex being equal to the number of views in at least two views being generated. The method further includes storing the processed primitive data in a buffer. Finally, the processed primitive data may be read from the buffer for each view in the at least two views and transmitted to a raster pipeline to generate image data corresponding to a particular view.Type: GrantFiled: May 5, 2016Date of Patent: September 4, 2018Assignee: NVIDIA CorporationInventors: Ziyad Sami Hakura, Eric B. Lum, Henry Packard Moreton, Emmett M. Kilgariff
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Patent number: 10061526Abstract: One embodiment of the present invention is a memory subsystem that includes a sliding window tracker that tracks memory accesses associated with a sliding window of memory page groups. When the sliding window tracker detects an access operation associated with a memory page group within the sliding window, the sliding window tracker sets a reference bit that is associated with the memory page group and is included in a reference vector that represents accesses to the memory page groups within the sliding window. Based on the values of the reference bits, the sliding window tracker causes the selection a memory page in a memory page group that has fallen into disuse from a first memory to a second memory. Because the sliding window tracker tunes the memory pages that are resident in the first memory to reflect memory access patterns, the overall performance of the memory subsystem is improved.Type: GrantFiled: May 31, 2016Date of Patent: August 28, 2018Assignee: NVIDIA CORPORATIONInventors: John Mashey, Cameron Buschardt, James Leroy Deming, Jerome F. Duluk, Jr., Brian Fahs
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Patent number: 10062142Abstract: Data transfer techniques include transferring display surface data from a memory subsystem into a stutter buffer at a first rate until the stutter buffer is substantially full. The memory interface and/or memory of the memory subsystem may then be placed into a suspend state until the stutter buffer is substantially empty. The display surface data is transferred from the stutter buffer to display logic at a second rate even when the memory subsystem is in a suspend state. The second rate, which is typically the rendering rate of the display, is substantially slower than the rate at which data is transferred into the stutter buffer.Type: GrantFiled: December 31, 2012Date of Patent: August 28, 2018Assignee: NVIDIA CORPORATIONInventors: Rupesh Shah, Tyvis Cheung, Thomas Edward Dewey, Chris Cheng, Franciscus Sijstermans
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Patent number: 10055883Abstract: A method, computer readable medium, and system are disclosed for rendering shadows. A frustum projected from a grid cell corresponding to a light source in light-space is defined and a graphics primitive is determined to intersect the frustum. A light-space visibility buffer is accessed to obtain a set of pixel fragment footprints corresponding to the frustum and it is identified whether each pixel fragment footprint of the pixel fragment footprints is shadowed by the graphics primitive.Type: GrantFiled: January 6, 2016Date of Patent: August 21, 2018Assignee: NVIDIA CORPORATIONInventors: Christopher Ryan Wyman, Aaron Eliot Lefohn, Anjul Patney
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Patent number: 10057849Abstract: A system for, and method of, reducing power consumed obtaining system information from a cell, the system information contained in at least a master information block, a scheduling information block and a system information block. In one embodiment, the system includes: (1) a broadcast control channel (BCCH) frame cache configured to buffer received BCCH frames bearing portions of the system information and (2) a system information verifier associated with the BCCH frame cache and configured to determine version consistency in the master information block and the scheduling information block by employing the check numbers associated therewith.Type: GrantFiled: June 2, 2015Date of Patent: August 21, 2018Assignee: Nvidia CorporationInventors: Timothy Rogers, Rene-Cedric Vanderbergh
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Patent number: 10055875Abstract: One embodiment of the present invention sets forth an Eulerian fluid simulation technique which enables real-time simulations of large scale three dimensional fluid volumes that include free surface water. A hybrid grid representation composed of regular cubic cells on top of a layer of tall cells is used to reduce computation time. Water above an arbitrary terrain can be represented without consuming an excessive amount of memory and compute power, while focusing simulation effort on the area near the surface of the water to produce accurate results. Additionally, the grid representation may be optimized for a graphics processor implementation of the fluid solver.Type: GrantFiled: July 20, 2012Date of Patent: August 21, 2018Assignee: NVIDIA CORPORATIONInventors: Nuttapong Chentanez, Matthias Müller-Fischer
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Patent number: 10055806Abstract: A tile coalescer within a graphics processing pipeline coalesces coverage data into tiles. The coverage data indicates, for a set of XY positions, whether a graphics primitive covers those XY positions. The tile indicates, for a larger set of XY positions, whether one or more graphics primitives cover those XY positions. The tile coalescer includes coverage data in the tile only once for each XY position, thereby allowing the API ordering of the graphics primitives covering each XY position to be preserved. The tile is then distributed to a set of streaming multiprocessors for shading and blending operations. The different streaming multiprocessors execute thread groups to process the tile. In doing so, those thread groups may perform read-modify-write operations with data stored in memory. Each such thread group is scheduled to execute via atomic operations, and according to the API order of the associated graphics primitives.Type: GrantFiled: October 27, 2015Date of Patent: August 21, 2018Assignee: NVIDIA CORPORATIONInventors: Ziyad Hakura, Eric Lum, Dale Kirkland, Jack Choquette, Patrick R. Brown, Yury Y. Uralsky, Jeffrey Bolz