Patents Assigned to NVidia
  • Patent number: 10026468
    Abstract: This description is directed to a dynamic random access memory (DRAM) array having a plurality of rows and a plurality of columns. The array further includes a plurality of cells, each of which are associated with one of the columns and one of the rows. Each cell includes a capacitor that is selectively coupled to a bit line of its associate column so as to share charge with the bit line when the cell is selected. There is a segmented word line circuit for each row, which is controllable to cause selection of only a portion of the cells in the row.
    Type: Grant
    Filed: February 10, 2017
    Date of Patent: July 17, 2018
    Assignee: NVIDIA CORPORATION
    Inventor: William James Dally
  • Patent number: 10027893
    Abstract: Real-time video stabilization for mobile devices based on on-board motion sensing. In accordance with a method embodiment of the present invention, a first image frame from a camera at a first time is accessed. A second image frame from the camera at a subsequent time is accessed. A crop polygon around scene content common to the first image frame and the second image frame is identified. Movement information describing movement of the camera in an interval between the first time and the second time is accessed. The crop polygon is warped to remove motion distortions of the second image frame is warped using the movement information. The warping may include defining a virtual camera that remains static when the movement of the camera is below a movement threshold. The movement information may describe the movement of the camera at each scan line of the second image frame.
    Type: Grant
    Filed: May 10, 2016
    Date of Patent: July 17, 2018
    Assignee: Nvidia Corporation
    Inventors: Steven Bell, Alejandro Troccoli, Kari Pulli
  • Patent number: 10027401
    Abstract: A wireless communications system is described which comprises a base station, a relay device, and a terminal device. The terminal device is operable to transmit a message to the base station via the relay device. The relay device is operable to add a relay header to the message received from the terminal device, the relay header comprising control information for controlling the transmission of subsequent messages from the terminal device to the relay device. The relay device is also operable to relay the message having the relay header added to the base station. By adding such control information to messages being relayed from the terminal device to the base station on the uplink, subsequent downlink communications from the base station to the terminal device can include the control information generated at the relay device (or transmission parameters derived from the control information).
    Type: Grant
    Filed: August 17, 2012
    Date of Patent: July 17, 2018
    Assignee: Nvidia Corporation
    Inventors: Timothy James Speight, Paul William Piggin
  • Patent number: 10026223
    Abstract: Systems and methods of extracting an isosurface wherein points on the isosurface have a constant value. The method includes dividing a volume into a grid of voxels The method includes identifying intersecting edges in the voxels, wherein the intersecting edges intersect the isosurface. The method includes generating patches for the intersecting edges and tessellating the patches and generating a grid of tessellated vertices. The method includes determining intersection points of the tessellated vertices with the isosurface and moving the intersected vertices to form a finer approximation of the isosurface.
    Type: Grant
    Filed: November 5, 2014
    Date of Patent: July 17, 2018
    Assignee: Nvidia Corporation
    Inventor: Simon Green
  • Patent number: 10026140
    Abstract: A graphics system is disclosed. The graphics system includes at least one GPU (graphics processing unit) for processing a compute workload. The graphics system uses a multi-user manager for allocating the compute workload capability for each one of a plurality of users. Each user will use an access terminal.
    Type: Grant
    Filed: March 1, 2009
    Date of Patent: July 17, 2018
    Assignee: Nvidia Corporation
    Inventor: Michael Diamond
  • Patent number: 10025879
    Abstract: A system, computer readable medium, and method are disclosed for performing a tree traversal operation. The method includes the steps of executing, via a processor, a tree traversal operation for a tree data structure, receiving a transformation node that includes transformation data during the tree traversal operation, and transforming spatial data included in a query data structure based on the transformation data. Each node in the tree data structure is classified according to one of a plurality of nodesets, the plurality of nodesets corresponding to a plurality of local coordinate systems. The processor may be a parallel processing unit that includes one or more tree traversal units, which implement the tree traversal operation in hardware, software, or a combination of hardware and software.
    Type: Grant
    Filed: April 27, 2015
    Date of Patent: July 17, 2018
    Assignee: NVIDIA Corporation
    Inventors: Tero Tapani Karras, Samuli Matias Laine, Timo Oskari Aila
  • Patent number: 10020871
    Abstract: A wireless communications system is described which comprises a base station, a relay device, and a terminal device. The terminal device is operable to transmit a message to the base station via the relay device. The relay device is operable to add a relay header to the message received from the terminal device, the relay header comprising control information for controlling the transmission of subsequent messages from the terminal device to the relay device. The relay device is also operable to relay the message having the relay header added to the base station. By adding such control information to messages being relayed from the terminal device to the base station on the uplink, subsequent downlink communications from the base station to the terminal device can include the control information generated at the relay device (or transmission parameters derived from the control information).
    Type: Grant
    Filed: August 17, 2012
    Date of Patent: July 10, 2018
    Assignee: Nvidia Corporation
    Inventors: Timothy James Speight, Paul William Piggin
  • Patent number: 10019787
    Abstract: A solution is proposed that allows power savings via enhancement of pixel data to compensate for reducing backlight intensity levels. According to one embodiment, each pixel of a display is sorted according to the brightness (intensity) of the pixel. Regional pixel gains are calculated and applied on a per pixel basis so as not to exceed a quality threshold. The intensity of the backlight corresponding to each region may be decreased by an equivalent amount, thereby reducing (potentially significantly) the power consumed to operate the backlight while maintaining the color intensity in the image due to the applied pixel gains.
    Type: Grant
    Filed: April 4, 2013
    Date of Patent: July 10, 2018
    Assignee: Nvidia Corporation
    Inventors: David Wyatt, Arman Toorians
  • Patent number: 10020036
    Abstract: One embodiment of the present invention sets forth a method for accessing non-contiguous locations within a DRAM memory page by sending a first column address command to a first DRAM device using a first subset of pins and sending a second column address command to a second DRAM device using a second subset of repurposed pins. The technique requires minimal additional pins, space, and power consumption. Further, sending multiple column address commands allows for increased granularity of DRAM accesses and therefore more efficient use of pins. The technique for accessing non-contiguous locations within a DRAM memory page.
    Type: Grant
    Filed: December 12, 2012
    Date of Patent: July 10, 2018
    Assignee: NVIDIA CORPORATION
    Inventors: Alok Gupta, Wishwesh Gandhi, Ram Gummadi
  • Patent number: 10019776
    Abstract: A tile coalescer within a graphics processing pipeline coalesces coverage data into tiles. The coverage data indicates, for a set of XY positions, whether a graphics primitive covers those XY positions. The tile indicates, for a larger set of XY positions, whether one or more graphics primitives cover those XY positions. The tile coalescer includes coverage data in the tile only once for each XY position, thereby allowing the API ordering of the graphics primitives covering each XY position to be preserved. The tile is then distributed to a set of streaming multiprocessors for shading and blending operations. The different streaming multiprocessors execute thread groups to process the tile. In doing so, those thread groups may perform read-modify-write operations with data stored in memory. Each such thread group is scheduled to execute via atomic operations, and according to the API order of the associated graphics primitives.
    Type: Grant
    Filed: October 27, 2015
    Date of Patent: July 10, 2018
    Assignee: NVIDIA CORPORATION
    Inventors: Ziyad Hakura, Eric Lum, Dale Kirkland, Jack Choquette, Patrick R. Brown, Yury Y. Uralsky, Jeffrey Bolz
  • Patent number: 10019381
    Abstract: In one embodiment, a microprocessor is provided. The microprocessor includes a cache that is controlled by a cache controller. The cache controller is configured to replace cachelines in the cache based on a replacement scheme that prioritizes the replacement of cachelines that are less likely to cause roll back of a transaction of the microprocessor.
    Type: Grant
    Filed: May 1, 2012
    Date of Patent: July 10, 2018
    Assignee: Nvidia Corporation
    Inventor: Meng-Bing Yu
  • Patent number: 10013290
    Abstract: A system and method are provided for synchronizing threads in a divergent region of code within a multi-threaded parallel processing system. The method includes, prior to any thread entering a divergent region, generating a count that represents a number of threads that will enter the divergent region. The method also includes using the count within the divergent region to synchronize the threads in the divergent region.
    Type: Grant
    Filed: September 10, 2012
    Date of Patent: July 3, 2018
    Assignee: Nvidia Corporation
    Inventor: Stephen Jones
  • Patent number: 10013940
    Abstract: A method for refreshing a display. The method includes refreshing even and odd columns of a display panel at a first frame refresh rate where for each frame, even and odd columns are refreshed. Upon entering a display idle period, a low power display refresh is performed. The low power display refresh includes: refreshing the even columns of the display during even frames while circuitry driving odd columns are not used, and refreshing the odd columns of the display during odd frames while circuitry driving the even columns are not used. Refreshing the even columns and refreshing the odd columns are performed at a second frame refresh rate that is slower than the first frame refresh rate.
    Type: Grant
    Filed: December 31, 2012
    Date of Patent: July 3, 2018
    Assignee: Nvidia Corporation
    Inventor: David Wyatt
  • Patent number: 10008034
    Abstract: A system, method, and computer program product are provided for computing indirect lighting in a cloud network. In operation, one or more scenes for rendering are identified. Further, indirect lighting associated with the one or more scenes is identified. Additionally, computation associated with the indirect lighting is performed in a cloud network utilizing at least one of a voxel-based algorithm, a photon-based algorithm, or an irradiance-map-based algorithm.
    Type: Grant
    Filed: October 18, 2013
    Date of Patent: June 26, 2018
    Assignee: NVIDIA Corporation
    Inventors: Morgan McGuire, Cyril Jean-Francois Crassin, David Patrick Luebke, Michael Thomas Mara, Brent L. Oster, Peter Schuyler Shirley, Peter-Pike J. Sloan, Christopher Ryan Wyman
  • Patent number: 10009027
    Abstract: Three state latch. In accordance with a first embodiment, an electronic circuit includes n pairs of cascaded logical gates. Each of the n pairs of cascaded logical gates includes a first logical gate including n?1 first gate inputs and one first gate output, and a second logical gate including two second gate inputs and one second gate output. One of the second gate inputs is coupled to the first gate output. The second gate output is cross coupled to one of the first gate inputs of all other the pairs of cascaded logical gates, and n is greater than 2.
    Type: Grant
    Filed: March 31, 2017
    Date of Patent: June 26, 2018
    Assignee: NVIDIA Corporation
    Inventors: Andreas J. Gotterba, Jesse S. Wang
  • Patent number: 10008029
    Abstract: Updating depth related graphics data is described. Geometric primitives are processed. Pixels are generated from the primitives based on the processing, each of which has at least one corresponding depth value. Culling is performed on a first group of the pixels, based on a representation of the at least one depth related value corresponding to each. Pixels may be discarded based on the culling and upon which a second group of pixels remain. A depth related raster operations function is performed, in which data is transacted with a depth buffer. The culling function is updated in relation to the transacting. The updating is performed on the basis of a granularity, which characterizes the culling function.
    Type: Grant
    Filed: May 31, 2013
    Date of Patent: June 26, 2018
    Assignee: Nvidia Corporation
    Inventors: Christian Amsinck, Eric B. Lum, Barry Rodgers, Tony Louca, Christian Rouet, Jonathan Dunaisky
  • Patent number: 10008033
    Abstract: A method, system, and computer program product for performing a lighting simulation are disclosed. The method includes the steps of receiving a three-dimensional (3D) model, receiving a set of probes, where each probe specifies a location within the 3D model and an orientation of the probe, and performing, via a processor, a lighting simulation based on the 3D model, the set of probes, and one or more light path expressions. The light path expressions are regular expressions that represent a series of events, each event representing an interaction of a ray at a location in the 3D model.
    Type: Grant
    Filed: January 2, 2018
    Date of Patent: June 26, 2018
    Assignee: NVIDIA Corporation
    Inventors: Daniel Johannes Seibert, Stefan Radig, Matthias Raab, Carsten Alexander Wächter, Lutz Kettner, Alexander Keller, Dirk Gerrit van Antwerpen
  • Patent number: 10008043
    Abstract: In embodiments of the invention, an apparatus may include a display comprising a plurality of pixels and a computer system coupled with the display and operable to instruct the display to display images. The apparatus may further include an SLM array located adjacent to the display and comprising a plurality of SLMs, wherein the SLM array is operable to produce a light field by altering light emitted by the display to simulate an object that is in focus to an observer while the display and the SLM array are located within a near-eye range of the observer.
    Type: Grant
    Filed: November 14, 2016
    Date of Patent: June 26, 2018
    Assignee: NVIDIA CORPORATION
    Inventors: David Luebke, Douglas Patrick Lanman, Thomas Francis Fox, Gerrit Slavenburg
  • Patent number: 10007527
    Abstract: One embodiment of the present invention sets forth a technique for processing load instructions for parallel threads of a thread group when a sub-set of the parallel threads request the same memory address. The load/store unit determines if the memory addresses for each sub-set of parallel threads match based on one or more uniform patterns. When a match is achieved for at least one of the uniform patterns, the load/store unit transmits a read request to retrieve data for the sub-set of parallel threads. The number of read requests transmitted is reduced compared with performing a separate read request for each thread in the sub-set. A variety of uniform patterns may be defined based on common access patterns present in program instructions. A variety of uniform patterns may also be defined based on interconnect constraints between the load/store unit and the memory when a full crossbar interconnect is not available.
    Type: Grant
    Filed: March 5, 2012
    Date of Patent: June 26, 2018
    Assignee: NVIDIA CORPORATION
    Inventors: Michael Fetterman, Stewart Glenn Carlton, Douglas J. Hahn, Rajeshwaran Selvanesan, Shirish Gadre, Steven James Heinrich
  • Patent number: 10009606
    Abstract: A technique for decoding data within a context-based adaptive binary arithmetic coding (CABAC) stream processes one or more bins of compressed data based on video format parameters associated with the stream. A configurable CABAC decoder circuit cascades one or more instances of CABAC bin decoder logic to operate properly within a timing constrain established by a decoder clock frequency. The decoder may advantageously select among different combinations of decoder clock frequency and decoded bins per clock cycle to minimize power consumption associated with decompressing and playing the compressed data.
    Type: Grant
    Filed: October 11, 2012
    Date of Patent: June 26, 2018
    Assignee: NVIDIA Corporation
    Inventors: Ravi Bulusu, Harikrishna Reddy