Abstract: A membrane for an acoustic transducer is provided which comprises a first portion having a first stiffness, and a second portion comprising a first subsection having a second stiffness and a second subsection having a third stiffness, wherein the second stiffness and the third stiffness are different.

Abstract: Data such as image, sound or other media content is delivered between peer devices over a dedicated peer-to-peer communications medium. According to an example embodiment, data is communicated between peer devices respectively belonging to one of a plurality of device classes respectively identified by a device-class identification (ID). Data is stored to identify communications that are to be carried out between devices having respective IDs, such that each pair of IDs has predefined execution steps based upon operational status of the devices. Based upon the device-class ID pair of two peer devices and an operating status of one or both devices, the devices automatically select and execute a communications approach to communicate data therebetween. This communication can be effected in response to a simple user input (e.g., which is specific to neither data nor transfer direction).

Abstract: A microelectronic package assembly comprises a lead frame having a holding bar (16) and a microelectronic package (14). The microelectronic package (14) comprises a package body (22) and a connecting element (24) for connecting the package body (22) to the holding bar (16) of the lead frame (12). The connecting element (24) extends from an outer surface (26) of the package body (22) and is engaged with an ending part (28) of the holding bar (16).

Abstract: A Static Random Access Memory comprising a matrix arrangement of cells, each cell comprising:—a bistable loop of a first inverter and a second inverter, in which an input of the first inverter is coupled to an output of the second inverter at a first bistable node and an input of the second inverter is coupled to an output of the first inverter at a second bistable node;—a first access transistor connected between the first bistable node and a write bitline, the first access transistor having a control terminal connected to a write wordline, and—a second access transistor connected between the second bistable node and a line being the complement of the write bitline, the second access transistor having a control terminal connected to the write wordline wherein—a first separate read port is connected between a read bitline and a source potential, which first read port has at least two control terminals, one control terminal being connected to the second bistable node and one to a read wordline, and—a second se

Abstract: The invention relates to a method of determining a charged particle concentration in an analyte (100), the method comprising steps of: i) determining at least two measurement points of a surface-potential versus interface-temperature curve (c1, c2, c3, c4), wherein the interface temperature is obtained from a temperature difference between a first interface between a first ion-sensitive dielectric (Fsd) and the analyte (100) and a second interface between a second ion-sensitive dielectric (Ssd) and the analyte (100), and wherein the surface-potential is obtained from a potential difference between a first electrode (Fe) and a second electrode (Se) onto which said first ion-sensitive dielectric (Fsd) and said second ion-sensitive dielectric (Ssd) are respectively provided, And ii) calculating the charged particle concentration from locations of the at least two measurement points of said curve (c1, c2, c3, c4).

Abstract: This invention relates to a method, a computer program product, a device, and a system, wherein a receiver unit (200,300,300?,500,500?,600,600?) is configured to operate in a single-channel mode and in a multi-channel mode, wherein in the single-channel mode the receiver unit (200,300,300?,500,500?,600,600?) is configured to output exactly one channel of a received signal, and in the multiple-channel mode the receiver unit (200,300,300?,500,500?,600,600?) is configured to output at least two channels of the received signal.

Abstract: A novel Si MEMS piezoresistive resonator is described. The resonator has a shape of a frame, such as a ring or a polygon frame, which has two or more anchors. Electrodes located at the outer or inner rim of the resonant structure are used to excite the structure electrostatically into resonance with a desired mode shape. One or plurality of locally doped regions on the structure is used for piezoresistive readout of the signal. In the most preferred embodiments, the structure is a ring, which has four anchors, two electrodes and four piezoresistive regions at different segments of the structure. The piezoresistive regions are alternatively located at the outer rim and inner rim of the structure in such a way that the piezoresistive signals of the same sign from different regions can be collected. Advantages of this device are large readout signal, large electrode area, robustness, suppressed out-of-plane vibration and larger usable linear range.

Abstract: A biocompatible electrode is manufactured by depositing filling metal 36 and etching back the filling metal to the surface of the surrounding insulator 30. Then, a further etch forms a recess 38 at the top of the via 32. An electrode metal 40 is then deposited and etched back to fill the recess 38 and form biocompatible electrode 42. In this way, a planar biocompatible electrode is achieved. The step of etching to form the recess may be carried out in the same CMP tool as is used to etch back the filling metal 36. A hydrogen peroxide etch may be used.

Abstract: The present invention relates to an electronic component, that comprises, on a substrate, at least one integrated MIM capacitor, (114) an electrically insulating first cover layer (120) which partly or fully covers the top capacitor electrode (118) and is made of a lead-containing dielectric material, and a top barrier layer (122) on the first cover layer. The top barrier layer serves for avoiding a reduction of lead atoms comprised by the first cover layer under exposure of the first cover layer to a reducing substance. An electrically insulating second cover layer (124) on the top barrier layer has a dielectric permittivity smaller than that of the first cover layer establishes a low parasitic capacitance of the cover-layer structure. The described cover-layer structure with the intermediate top barrier layer allows to fabricate a high-accuracy resistor layer (126.1) on top.

Abstract: A microphone system is provided, wherein the microphone system comprises a microphone array comprising a plurality of microphone units each adapted to generate a primary signal indicative of an acoustic wave received from the respective microphone unit, a first echo cancellation unit, an integrator unit, and a combination unit, wherein the microphone system is adapted to generate a first dipole response and a monopole response from the primary signals, wherein the integrator unit is adapted to generate a first integrated dipole response by integrating the first dipole response, wherein the first echo cancellation unit is adapted to generate a first echo cancelled integrated dipole response from the first integrated dipole response, and wherein the combination unit is adapted to combine the monopole response and the first echo cancelled integrated dipole response.

Abstract: The invention relates to an integrated Doherty amplifier with an input network connecting the input to the main stage and to the peak stage, and with an output network connecting the main stage and the peak stage to the output. The output network has a shunt capacitor to signal-ground in parallel to a parasitic capacitance of the main stage, and has a shunt inductor between the main stage and signal ground. The shunt configuration enables to use the MMIC Doherty amplifier in a wide frequency range. At least some of the inductors of the input network and/or output network are implemented using bond wires. Their orientations and locations provide minimal mutual electromagnetic coupling between the wires and the return RF current paths.

Abstract: A power island for a system-on-a-chip (SoC) includes a first segment, a second segment, and a supply line. The first segment includes a hardware device and operates the hardware device at first power characteristics indicative of at least a first voltage. The second segment includes scalable logic and operates the scalable logic at second power characteristics indicative of at least a second voltage. The second power characteristics of the scalable logic are different from the first power characteristics of the hardware device. The supply line receives an external supply signal (VDD) and directs the external supply signal to both the first segment and the second segment. The second segment changes at least one power characteristic of the external supply signal to operate the scalable logic according to the second power characteristics.

Abstract: The present invention relates to a circuit arrangement, which is used for controlling a high side CMOS transistor (M1) in a high voltage deep sub micron process. To provide a circuit arrangement for switching a high side CMOS transistor (M1) in a circuit having a very thin gate oxide, produced by a deep sub micron process, a circuit arrangement is proposed for controlling a high side CMOS transistor (M1), wherein the high side CMOS transistor (M1) is coupled between a high side voltage potential (Vbat) and a control output (OUT) for switching an external device, the high side CMOS transistor (M1) is controlled at its gate by a reference potential (Vbat-Vref), which is provided by a high side voltage reference (11) having a capacitor (C1), which is charged for switching on and discharged for switching off the high side CMOS transistor (M1).

Abstract: The invention relates to a circuit arrangement (30, 40, 70, 80, 90) of a low-noise linear input amplifier comprising a parallel circuit of a common-base circuit (20) and a common-emitter circuit (30), the emitters of two first transistors (Q3, Q4) are interlinked and the bases of two second transistors (Q1, Q2) are intercoupled, the collectors are interconnected in parallel with the output, and the source voltage (VG) is interlinked with the emitters of the second transistors (Q1, Q2) and with the bases of the first transistors (Q3, Q4), in which a linearization of the output current (OUTLNA1,2) as a function of the source voltage (VG) is achieved by a linearization of the transfer function, such as the tangential hyperbolic function, of the first and second transistors (Q1, Q2, Q3, Q4).

Abstract: An ADC is disclosed which has, as a first stage, a successive approximation converter, or other compensated, direct comparison converter, followed by a sigma delta modulation converter as a second stage. The sigma delta converter may beneficially be a first order modulator. The resulting ADC combines accuracy with low power consumption per conversion, and thus is particularly suited for use in temperature sensors for applications such as RFID transponders. Such a temperature sensor and an RFID transponder are also disclosed. There is also disclosed a method of analog-to-digital conversion, comprising a first successive approximation register or other compensated, direct comparison conversion stage followed by a sigma delta modulation stage, which, further, may be combined with providing a proportional-to-absolute-temperature (PTAT) signal, for low-power, accurate temperature sensing.

Abstract: A signal processor for removing at least one unintended signal component from an input signal (ua) is proposed. The signal processor includes a filter device (130) and a processing device (150). The filter device (130) filters the input signal (uâ) and generates a filtered signal (uf), which includes the unintended signal component to be removed. The processing device (150) generates an output signal (um), which indicates a deviation of the input signal (ua) from the filtered input signal (uf). By detecting the unintended signal component first an removing this component from the input signal (uâ), the input signal will not be manipulated directly but the unintended signal component in the input signal (uâ) will be compensated. This allows to remove the unintended component from the input signal (uâ) with less distortions of the interesting components in the input signal (uâ).

Abstract: The present invention relates to an electric component comprising at least one first MIM capacitor having a ferroelectric insulator with a dielectric constant of at least 100 between a first capacitor electrode of a first electrode material and a second capacitor electrode of a second electrode material. The first and second electrode materials are selected such that the first MIM capacitor exhibits, as a function of a DC voltage applicable between the first and second electrodes, an asymmetric capacity hysteresis that lets the first MIM capacitor, in absence of the DC voltage, assume one of at least two possible distinct capacitance values, in dependence on a polarity of a switching voltage last applied to the capacitor, the switching voltage having an amount larger than a threshold-voltage amount. The invention is applicable for ESD sensors, memories and high-frequency devices.

Abstract: A method of calibrating a pipelined analog to digital converter (400) having a plurality of DAC elements (410) and an additional calibration DAC element (420), in which a combination of positive, negative and zero reference voltages to the element under calibration and positive and negative reference voltages to the additional calibration DAC element to obtain four calibration states from which an error of the element under calibration is extracted by calculating an average of the difference between the four calibration states.

Abstract: Disclosed is a method of forming a heterojunction bipolar transistor (HBT), comprising depositing a first stack comprising an polysilicon layer (16) and a sacrificial layer (18) on a mono-crystalline silicon substrate surface (10); patterning the first stack to form a trench (22) extending to the substrate; depositing a silicon layer (24) over the resultant structure; depositing a silicon-germanium-carbon layer (26) over the resultant structure; selectively removing the silicon-germanium-carbon layer (26) from the sidewalls of the trench (22); depositing a boron-doped silicon-germanium-carbon layer (28) over the resultant structure; depositing a further silicon-germanium-carbon layer (30) over the resultant structure; depositing a boron-doped further silicon layer (32) over the resultant structure; forming dielectric spacers (34) on the sidewalls of the trench (22); filling the trench (22) with an emitter material (36); exposing polysilicon regions (16) outside the side walls of the trench by selectively remo

Abstract: A system implements a secure transaction of data between a server and a remote device. The remote device comprises: processing means adapted to process input data according to a security process; data storage means adapted to store verification information derived from the input data according to an encryption algorithm; and communication means for communicating the input data which has been processed by the security process to the server. The server is adapted to transmit a verification request to the remote device, and to verify the integrity of the security process based on verification information received from the communication means of the remote device in response to the verification request.