Abstract: A processing circuit has functional units (10a-c) configured to perform operations each in response to a respective command. The functional units (10a-c) are configured to execute at least one of the operations with a selectable level of susceptibility to incurring an error during execution. Different functional units may be provided, designed to execute the same operation with different levels of susceptibility at the cost of more circuit area, power consumption or execution time in the case of less susceptibility. The less susceptible functional unit may comprise additional error correction circuits, or more pipeline stages for example. The program directs commands to execute the operation to different functional units according to the required level of susceptibility. High level programs may be provided wherein variables are declared with a specified level of reliability. These declarations may be used during compilation to select how instructions will be executed.

Abstract: A translation lookaside buffer (TLB) is disclosed formed using RAM and synthesisable logic circuits. The TLB provides logic within the synthesisable logic for pairing down a number of memory locations that must be searched to find a translation to a physical address from a received virtual address. The logic provides a hashing circuit for hashing the received virtual address and uses the hashed virtual address to index the RAM to locate a line within the RAM that provides the translation.

Abstract: A multi-issue processor includes a register file and a plurality of issue slots, each one of the plurality of issue slots having a plurality of functional units and a plurality of holdable registers. The plurality of issue slots include a first set of issue slots and a second set of issue slots, and the register file is accessible by the plurality of issue slots. A location of at least a part of the plurality of holdable registers in the first set of issue slots is different from a location of at least a corresponding part of the plurality of holdable registers in the second set of issue slots.