Abstract: Memory requirements in a video processor and display system are reduced by storing in memory processed video signals for a plurality of regions of a picture, processing video signals for additional regions of a picture while stored video signals are retrieved in controlling a display, and then storing the newly processed video signals in the memory space occupied by the retrieved video signals. An entire reconstructed frame of image signals is not needed in order to begin the display of the same frame, certain regions of the frame can be displayed while other regions are still being reconstructed. Overwrite protection is provided for stored image signals until the stored image signals are retrieved for image display.

Abstract: A method for preserving data through a softboot process is presented. Areas in a device DRAM are reserved for data structures generated during execution of a boot code stored in the device ROM. A communications channel between the device and an external device is established and data structures related to the communications channel status and startup diagnostics are written to reserved areas of DRAM. Firmware stored on an external device is downloaded to a different area of DRAM. After a softboot, the data structures in DRAM are accessed by firmware enabling the communications channel to be maintained and startup diagnostics data to be utilized.

Abstract: The present invention simulates the behavior of a storage component by first determining whether a timing violation has occurred for the storage component. If one or more timing violations is detected, then an x (indicating uncertainty) is reflected at the output of the storage component. This x is maintained at the output of the storage component for a predetermined number of timing units. After the predetermined number of timing units has expired, the output of the storage component is changed from x to a certain value, such as a logical 1 or a logical 0. By changing the output to a certain value, the present invention prevents the x at the output of the storage component from indefinitely propagating to other components in the circuit. This in turn prevents large numbers of x's from appearing in the simulation results provided to the designer. Instead, values that are certain will appear in the results.

Abstract: A computer system or computer system main memory is provided. The computer system includes a secondary memory and a buffer. The buffer is one having a faster access time than the secondary memory, and data placed within the buffer can be controlled by a control block configured with a control field and a byte count value of data bytes transferred during a DMA cycle, or a chain of DMA cycles. A counter may be used to increment the byte count within one or more control blocks during transfer of data bytes from secondary memory to the buffer. A requester is coupled to forward a read request that is serviced from the buffer if an address of the read request is included within an address incremented by the byte count. Both the control blocks and the buffer can be contained within a main memory local to the requester.

Abstract: A computer system, bus interface unit, and method is provided for noting a control block transfer at which an interrupt occurs. The control block is but one control block within a chain of control blocks necessary to effectuate a chain of DMA transfers. If the control block undergoes an interrupt, that control block must be noted and control information associated therewith placed within a register so that when the DMA transfers are resumed, that control block can be immediately pointed to rather than having to initiate the first control block of the chain up to and including the control block undergoing interrupt. By purposely programming interrupts within the tag field of select control blocks and maintaining a software tag register within system memory, a control block within an expanded number of control blocks within a chain can be kept track of and pointed to following an error-induced interrupt.

Abstract: A method and apparatus for processing data read from a DVD media containing stored data is described. The apparatus includes a DVD media reader for reading data and error information stored on a DVD media, an error processor for determining the number of errors in the read data, and a display means for displaying the number of errors. The method includes the steps of reading actual data from a DVD media, computing a first correction code for the actual data, reading a second correction code from the DVD media, the second correction code pertaining directly to said stored data, and comparing the first and second correction codes to determine whether said actual data needs to be corrected. The method further includes the steps of determining whether the number of errors in the actual data exceeds the number of errors that can be corrected, correcting the actual data if possible, and counting the number of errors that are corrected.