Abstract: A method of adaptive spatial filtering for enhancing digital images is presented. A window is applied to a source pixel to generate an array of windowed pixels. An upper threshold value and lower threshold value corresponding to the maximum and minimum pixel values, respectively, in the array of windowed pixels are determined. A spatial frequency filter is applied to the array of windowed pixels to generate a filtered array of pixels including a reference pixel. The values of the source pixel and the reference pixel are scaled by respective weighting factors and then combined to create an enhanced pixel value. If the enhanced pixel value exceeds the upper threshold value, the enhanced pixel value is replaced by the upper threshold value. Similarly, if the enhanced pixel value is less than the lower threshold value, the enhanced pixel value is replaced by the lower threshold value.

Abstract: The present invention is directed to a method of discriminating between textual content and graphical content. The method includes the steps of receiving a plurality of pixel values for a pixel line segment, calculating a plurality of spatial gradients based on the pixel values of adjacent pixels, determining a smoothness index by processing the plurality of spatial gradients, and identifying the pixel line segment as text or graphics by comparing the smoothness index to a threshold value.

Abstract: An apparatus for estimating values for Eight-Fourteen Modulated (EFM) data includes a peak detector and modification circuitry. The peak detector receives a first set of signals representing initial values of a sequence of EFM datums, each of which has an initial value that is a member of a first set of values including {−b, −a, c, a, b} where |b|>|a|>|c|. The peak detector analyzes a first subsequence of the sequence of EFM datums to determine whether a peak has occurred and, if so, asserts a modify signal. The modification circuitry responds to assertion of the modify signal by replacing the initial values of a second subsequence of the sequence EFM datums with revised values. The second subsequence of EFM datums follows the first subsequence of EFM datums and each revised value of the second subsequence has an absolute value that is a member of the first set of values.

Abstract: A wavelet transform system and an inverse wavelet transform system are disclosed that respectively implement a wavelet transform and an inverse wavelet transform. Semi-orthogonal standard wavelets are used as the basic wavelets in the wavelet transform and the inverse wavelet transform. As a result, two finite sequences of decomposition coefficients are used for decomposition in the wavelet transform. Furthermore, two finite sequences of reconstruction coefficients that are derived from the two finite sequences of decomposition coefficients are used for reconstruction in the inverse wavelet transform. The finite sequences of decomposition and reconstruction coefficients are not infinite sequences of coefficients that have been truncated. Furthermore, in one embodiment, downsampling is not used in the wavelet transform and upsampling is not used in the inverse wavelet transform.

Abstract: Method and system for receiving each data element of an array once and simultaneously forming an EDC error detection term, two ECC P-parity checkbytes and two ECC-Q-parity checkbytes for the array. Each data element is read once from memory and is received by an EDC processor, by an ECC-P processor and by an ECC-Q processor and is processed in parallel and substantially simultaneously by the three processors to form an EDC error detection term and the ECC-P-parity and ECC-Q-parity checkbytes, using shift registers with feed-back and/or weighted summation of selected register contents.

Abstract: A subcode processing circuit of an optical disc drive, and a method for processing subcode data are disclosed. The subcode processing circuit includes a shift register circuit for processing a plurality of standard subcode data bytes that are obtained from an optical disc media of the optical disc drive. The processing is configured to pack the plurality of standard subcode data bytes into a plurality of packed subcode data bytes. The plurality of packed subcode data bytes is configured to be less than the plurality of standard subcode data bytes. In one example, the shift register circuit is configured to include a plurality of shift registers and a multiplexer to assist in the processing. The subcode processing circuit is further configured to perform error correction for each byte of the plurality of packed subcode data bytes.

Abstract: A Finite Impulse Response filter (FIR) reduces the effect of baseline wandering of the input signal on convergence. The FIR includes an adder, a DC-Insensitive error calculator, a DC-Insensitive coefficient calculator, and a multiplier. The adder adds a first tap signal to a second tap signal to produce a FIR output signal. The DC-Insensitive error calculator calculates from the FIR output signal an error value that converges to zero while the FIR output signal is subject to baseline wandering. The DC-Insensitive error calculator represents the error value via an error signal. The DC-Insensitive coefficient calculator calculates a coefficient value based upon the error signal and an input signal. The DC-Insensitive coefficient calculator forces the coefficient value to converge to a steady state value while the input signal is subject to baseline wandering. The coefficient value is represented by a coefficient signal.

Abstract: A versatile serial to parallel interface capable of both receiving multiple types of input formats and operating in multiple operational modes includes a multiplexer, a signal generator, and a register. The multiplexer receives serial data from a plurality of possible data sources and, in response to a set of selection signals, outputs one of the sets of serial data to the signal generator. The signal generator thereafter forwards the serial data to the register for storage. In addition to forwarding the serial data to the register, the signal generator also generates clock and control signals. These signals are used to control the operation of the register to ensure proper serial to parallel conversion of the input serial data. In addition, these signals may also be provided to the source of the serial data to control the actions of the data source. The signal generator generates the clock and control signals in response to indication information provided to the signal generator.

Abstract: A mechanism for implementing fault tolerant logic in an information storage system is disclosed. The mechanism comprises an inhibit logic which is invoked when the first RUNOUT block of a link sequence is detected. Once invoked, the inhibit logic outputs a disable signal, and so long as the disable signal is asserted, certain control signals are inhibited. These control signals may include a trigger signal, a target match signal, and a miss signal. The disable signal is maintained during the reading of blocks, such as link sequence blocks, in which information corruption is most likely to occur. By doing so, the inhibit logic prevents erroneous signals generated as a result of corrupted information from adversely affecting the operation of the storage system. As a result, the corrupted information is tolerated.

Abstract: A compact disk drive controller to control the access of information from an optical compact disk (CD) digital data storage device by a host computer using an integrated drive electronics (IDE) data bus or an industry standard architecture (ISA) data bus is disclosed. A digital signal processor (DSP) interface to the drive electronics of the CD drive, a dynamic random access memory (DRAM) controller, an error correction code (ECC) data corrector, an error detection and correction (EDC) device employing cyclical redundancy checking techniques (EDC/CRC), and a host computer interface are described.

Abstract: An electronic system is described herein, the apparatus including at least two devices requiring access to memory, a memory controller, and a memory, the memory being coupled to an output of the memory controller. The memory controller includes at least one input and at least one output; one memory controller input being operatively coupled to at least one of the devices through a shared bus, and one memory controller output being operatively coupled to at least one device through a shared bus. The shared bus includes a plurality of device select lines, a plurality of address lines, a plurality of write data lines, a plurality of read data lines, a plurality of read select lines, and at least two device_request lines.

Abstract: The apparatus corrects a data detection error caused by baseline wandering in an optical PRML read channel. The apparatus includes error detection circuitry and error correction circuitry. The error detection circuitry monitors a serial output signal from the optical PRML read channel and a first set of input signals to the optical PRML read channel to detect an error event associated with baseline wandering. The error detection circuitry deems the error event to have occurred when three conditions are satisfied. First, a bit sequence represented by the serial output signal matches a first bit sequence associated with the error event. Second, a first difference in a first set of consecutive values represented by the first set of input signals is within a first range of values associated with the error event. Third, a second difference in a second set of consecutive values of the first input signal is within a second range of values associated with the error event.

Abstract: Method and system for receiving each data element of an N×M array once and simultaneously forming an EDC error detection term and two ECC P-parity checkbytes for the array. Each data element is read once from memory and is received by an EDC processor and by an ECC processor and processed in parallel by the two processors to form the EDC error detection term and two ECC P-parity checkbytes.

Abstract: Method and system for identifying and facilitating access to computer printouts contained in an array of printout bins. Each printout is provided with indicium information concerning the project and/or the user for whom the printout was prepared. When the printout is placed in a bin, the indicium information is entered and displayed adjacent to the printout bin. A user examines the bin displays, identifies the bin(s) containing the user's printout(s), removes the printout and advises the system that the printout has been removed. Thereafter, the display no longer includes indicium information for the removed printout. One or more bins for confidential printouts can be locked, with bin access allowed only if (1) acceptable confidential user identification is presented and (2) at least one printout for that user is presently contained in the locked bin. Indicium information can be communicated to the printout bin or to a project monitor independently of whether a printout is prepared.

Abstract: A parental management controller for use in a DVD environment is disclosed that defines, in a distributive computer environment, department, country, or corporate controls over DVD content viewed by machines within the environment. The controller provides automated parental management installation on remote machines. It provides parental management enforcement on remote machines. It adjusts the default parental management enforcement level to local cultures and moral values. The controller also provides a logging of any parental management violations on local machines.

Abstract: An interactive DVD browser in accordance with the DVD specification for read-only discs is capable of accessing remotely located data over the Internet through a technique which contemplates new navigation commands as well as the embedding of HTML page addresses in navigation commands in place of data stream identifiers currently unused by the DVD specification. A navigation command is supplied to the interactive DVD browser indicating the browser should change data sources. The navigation command includes a network protocol address, in the form of HTML page address, as well as a local address of the user's default Internet browser. A second command specifies a predetermined period of time in which the browser should wait until the Internet browser establishes a hyperlink to the remote source of presentation data specified by the network page address.

Abstract: A memory efficient method for translating and displaying sub-picture images for DVD data. The method uses less memory than prior systems. Rather than storing the sub-picture image in a memory, the method decodes and displays the sub-picture images on-the-fly. Subsequent sub-picture pixels are being translated as a given sub-picture pixel is being displayed on a display.

Abstract: Method and system for estimating an optimal power level for writing on a compact disk. Measured values m(Pi) of a modulation amplitude are approximated by a continuous function m(P)=1−A/(P−P0+B)C of power level P, where C=1 and B=A, and the parameter A is to be determined, or where all three parameters A, B and C are to be determined. A selected derivative of modulation amplitude, &ggr;=(P/m(P)·(dm/dP) is computed and analyzed to estimate a value of power level P corresponding to a specified value of &ggr;.

Abstract: A method for set-up of a group of parameter values needed in a CD-R or CD-RW write cycle, where the time allotted for set-up is as low as six clock cycles. In a clock cycle from a preceding write cycle, first and second parameter values are read into first and second registers, and a third parameter value is read into a first SRAM. In clock cycles 1-5 of the present write cycle, fourth, fifth, sixth, seventh and eighth parameter values are read into second, third, fourth, fifth and sixth SRAMs. In clock cycle no. 6 or later of the present write cycle, three sums (or differences) of selected combinations of these eight parameter values are calculated and stored, new first and second parameter values are read into first and second registers, and a new third parameter value is read into another SRAM. The method is generalized to K parameters stored in registers, N parameters stored in SRAMs and calculation of M selected linear combinations of the K+N parameter values.

Abstract: A method determines a power value for writing data on a disk. Write-patterns are written on the disk, and each write-pattern is written at an associated power value. For each write-pattern of at least a subset of the write-patterns, the write-pattern is read, a bit error corresponding to the write-pattern is determined to generate a calibration profile of associated bit errors and power values, and a selected power value is designated based on the calibration profile. In one embodiment, the selected power value is designated based on both the calibration profile and an asymmetry value associated with each write-pattern. In another embodiment, the selected power value is designated based on both the calibration profile and a gamma value associated with each write-pattern.