Abstract: An interface circuit that facilitates communication between a DSP and decoder in a disc system or other application. The interface circuit is programmable so multiple communication interfaces can be supported without requiring additional specialized logic uniquely tailored for each particular communication interface. Sector and countdown-type data transfers are supported by the interface circuit.

Abstract: A voice or data transmission system and specifically an interpolation filter used within the transmission system is provided for producing either fractional or integer interpolation ratios. The digital signal resulting from the interpolation filter has a relatively high signal to noise ratio whenever fractional interpolation is needed. The interpolation filter includes multiple stages coupled in series, and an integer interpolation branch switched in parallel with a fractional interpolation branch. A controller determines whether the integer or fractional interpolation ratio is needed based on maintaining a fixed oversampling data rate from the interpolation filter given a changing incoming sampling rate. If the incoming sampling rate should require fractional interpolation, then a branch implementing fractional interpolation ratio is used in lieu of the integer interpolation ratio.

Abstract: A multi-threaded digital versatile disc system which is controlled by a system thread includes an independent counter thread for controlling the counter parameters. Only the counter thread (and not the system thread) increments and decrements the counter parameters based on an input from the system clock. Counter parameters can be attached, or associated, with the counter thread and all associated counter parameters are incremented together by the thread. The counter thread has a semaphore and a queue associated with it and the counter thread remains dormant until woken up by the semaphore. The semaphore queue receives periodic messages from the system clock via a conventional operating system mechanism and periodically increments and decrements its associated counter parameters. Other threads, originating from this system or from another system, can also communicate with the counter thread by means of the queue by directing an event message to the operating system which places the message in the queue.

Abstract: A grayscale enhancement system which operates on color or monochrome source halftone images to produce output halftone cells of the same visual weight but spatially distributed to reduce artifacts caused by limited grayscale levels. By operating upon a set of input halftone cells surrounding each output pixel cell with a set of logic operations implementing unique algorithms, the system re-distributes the weight of the halftone cells characterizing inferred-halftone cells. A rendering subsystem, responsive to the inferred-halftones, then produces signal for driving an output device to the best of the output device's ability.

Abstract: An LBA/MSF converter includes a decade selector, the decade selector receiving a first input and generating a decade selector output corresponding to a decade of the first input. An operand selector receives the decade selector output and outputs an operand corresponding to the decade selector output. An adder outputs the sum of the first input and the operand, the sum being an MSF value corresponding to the first input when the first input is an LBA value, and a subtractor outputs the difference of the first input and the operand, the difference being an LBA value corresponding to the first input when the first input is an MSF value.

Abstract: An apparatus and a method to access data from a digital recording medium configured to store data in sectors delimited by a predetermined sequence of sync patterns. The apparatus includes a sync pattern detector and a sync sequence detector to detect whether a sequence of sync patterns detected by the sync pattern detector matches the predetermined sync pattern sequence. The sync sequence detector generates a sync error signal whenever a detected sync pattern fails to match an expected sync pattern taken from the predetermined sync pattern sequence. A sync error signal counter counts the number of sync error signals generated by the sync sequence detector and a comparator compares the number of sync error signals counted by the sync error signal counter with a sync error threshold, the comparator generating a disk error signal when the threshold is exceeded.

Abstract: A method and system of read-ahead caching for use in a DVD player utilizing CSS titles is disclosed. The caching system is a host-based read-ahead caching system that utilizes a threaded architecture for caching. One thread is dedicated to retrieving data from the cache and a second thread is dedicated to reading data from the cache. The producer thread is intelligent enough to cache only within a title boundary, thus preventing costly re-authentication steps.

Abstract: A multi-threaded digital versatile disc system which is controlled by a system thread includes an independent counter thread for controlling the counter parameters. Only the counter thread (and not the system thread) increments and decrements the counter parameters based on an input from the system clock. Counter parameters can be attached, or associated, with the counter thread and all associated counter parameters are incremented together by the thread. The counter thread has a semaphore and a queue associated with it and the counter thread remains dormant until woken up by the semaphore. The semaphore queue receives periodic messages from the system clock via a conventional operating system mechanism and periodically increments and decrements its associated counter parameters. Other threads originating from this system or from another system, can also communicate with the counter thread by means of the queue by directing an event message to the operating system which places the message in the queue.

Abstract: A semiconductor memory is partitioned into a predetermined number of sections. A first register stores dynamic values indicative of whether corresponding cells of the memory are defective, and includes an input terminal coupled to receive addresses from an associated address generator. A second register stores address mappings of corresponding pages in each of the partitioned sections, and includes an input terminal coupled to receive addresses from the address generator. A multiplexer includes first and second input terminals coupled to receive addresses from the address generator and mapped addresses from the second register, respectively, a control terminal coupled to receive the dynamic values from the first register, and an output terminal coupled to the address input lines of the memory. When the address generator generates a memory address in response to a request for instructions or data from an associated CPU, the first register checks whether the addressed memory location is defective.

Abstract: An apparatus and method for transferring a block of data between a first storage area in a first, unpacked format and a second, narrower storage area in a second, packed format. The present invention includes a set of working registers to temporarily store and manipulate portions of the block of data as it is transferred between the first and second storage areas. By employing this set of working registers, the present invention transfers blocks of data between the first and second storage areas with a low latency and the highest possible throughput.

Abstract: A computer system includes a host computer and a peripheral memory device such as a CD ROM which are interconnected by a bus including a plurality of pipes defined by packets, time division multiplexing, frequency division multiplexing, or code division multiplexing. A plurality of pipe configuration registers are maintained for controlling bus configuration. A BUS controller for the bus includes a plurality of registers for controlling data transfer including pipe data flow direction, packet size, control information, bandwidth setting, and descriptor pointer. The plurality of pipes can have different bandwidths and latencies to efficiently facilitate the transfer of commands, data, and control information. The peripheral memory device is able to transfer and receive data directly to and from the host computer using a dedicated pipe without the need of a buffer memory at the peripheral device.

Abstract: In a display system having a predefined number, n, of pixel types, a display processor, such as a digital versatile disc (DVD) display processor, includes a color palette which can store more than n color/contrast values and a subpicture bitmap composed of subpicture pixel values, each of which corresponds to one of the n pixel types. In a DVD display system, for example, the DVD subpicture pixel types are: Background, Pattern, Emphasis 1, and Emphasis 2. Each subpicture pixel value is, in turn, related to a color/contrast combination by the color palette, with each pixel value corresponding to the address of a palette location. The corresponding palette location contains the color/contrast value for the related subpicture pixel type. To modify the color/contrast value of a selected group of the pixels having one of the four DVD subpicture pixel types, the display processor updates the color palette, associating new color/contrast values with previously “unused” palette locations.

Abstract: An image processing system for performing rotation of an image reduces the size of the memory buffer needed for rotation while ensuring that rotation is compatible with a variety of compression techniques. A processing module determines whether a memory buffer sized to accommodate the entire image should be used, or whether a smaller memory buffer can be used to rotate smaller sized image sections. When the image data fills the selected memory buffer, rotation processing of the image data can then commence, regardless of whether the entire input image has been received by the processing module. A rotation module operates on incoming image data stored in the memory buffer, causing rotation of the image data and transfer to an encoder/decoder module where the image data is compressed in accordance with one or more compression techniques. After compression, the image data is stored in random memory locations.

Abstract: A clock generator for a PRML read channel for producing a clock signal with minimal jitter from an input signal subject to baseline wandering. The clock generator including a VGA amplifier, a low pass filter, an ADC, a baseline wander correction circuit, a timing offset detector and loop filter circuit, a DAC and a VCO. The VGA amplifier amplifies the input signal to produce a first analog signal. The low-pass filter filters the first analog signal to produce a second analog signal. The ADC converts the second analog signal into a first digital signal, operating synchronously with the clock signal. The baseline wander correction circuit reduces jitter in the clock signal caused by baseline wandering of the input signal. The baseline wander correction circuit produces a second digital signal from the first digital signal, operating synchronously with the clock signal. The second digital signal experiences substantially less baseline wandering than the first digital signal.

Abstract: A method and apparatus for optimizing the storage of compressed images includes serially storing pixel block data in memory. Fixed memory utilization can be improved for images having pixel blocks of varying information content. A cumulative memory allocation is updated during processing of each pixel block and compared with the current memory requirement. Memory not utilized for earlier processed pixel blocks having low information content can be used to store later processed high information content pixel blocks.

Abstract: A method and apparatus for dynamic chaining of DMA operations that includes a count to keep track of control blocks associated with such operations when appended to a current chain of control blocks. The count is checked by a DMA controller upon completing the data-transfer operation associated with each block or each control-block chain depending on the use of a wait bit. Memory used to hold control blocks may be preallocated with anticipated control blocks associated in a predefined linked list to avoid the need for subsequently updating existing control blocks when new blocks are appended to a chain.

Abstract: An improved burst mode for accessing a storage medium is provided which enables the storage medium to be accessed in any freely specifiable address increments/decrements. The accessing process begins with a bus arbiter receiving a set of request information from a host system specifying a starting address, an incremental/decremental (I/D) value, and a count n. These specified values are stored by the bus arbiter in an address register, an I/D register, and a count register, respectively. Then, the bus arbiter allows the host to access the storage medium beginning with the location having the address indicated by the value stored in the address register which, at this point, is the starting address specified by the host system. Once that location is accessed, the arbiter decrements the value in the count register by one. If the value in the count register is now equal to zero, the process stops.

Abstract: A system for avoiding overflow and underflow of image variables by clamping image gradients. The method is described with respect to a triangular polygon to be rendered, and a function for that polygon such as color. First the delta x and delta y values between each of the vertices of the triangle are computed. Using the delta x and delta y values, the area of the triangle is computed. The sign of the triangle area is used to determine whether the triangle is visible. If the triangle is visible then the method determines whether the width of the triangle in the x-direction, dx_min, is at least equal to a minimum threshold. To make this determination, first the vector with the largest delta y is selected. Using the largest delta y value, dx_min is computed. If dx_min is less than the threshold value, then a correction value is computed. The position of the vertex that is not part of the vector with the largest delta y is then corrected using the correction value.

Abstract: A method and system are disclosed for allowing selection of an icon most logically desired by the user in a graphic user interface when multiple icons are overlapping and the pointing device coordinates would force a given selection not desired by the user. A logical icon selector is provided that is coupled to the pointing device and provides a logic for selecting the desired icon based on proximity of the pointing device icon to the desired icon. Based on a calculation of the location of the overlapping icons to the pointing device icon, the icon having the closest proximity to the pointing device is selected.

Abstract: A technique to demodulate digital data streamed from a recording medium by periodically hashing m-bits of data to create an index to a look up table and a code word identifier. The look up table includes the modulation pattern, which has a plurality of m-bit data entries, mapped into a plurality of n-bit data clusters, with each of the plurality of data clusters including a sub-portion of one of the plurality of m-bit data entries and a cluster identifier, with each of the plurality of data clusters differing from the remaining data clusters, with n being less than mn. The index and code word identifier is determined from a sub-portion of the m-bits of data, which are then both compared with a sub-group of the plurality of data clusters. Upon finding a match between one of the data clusters of the subgroup and both the index and the code word identifier, a signal is generated.