Abstract: A PCIe bus extension system, method, interface card and cable for connecting a PCIe-compliant peripheral device to a PCIe bus of a computer system. The interface card includes a printed circuit board, an edge connector adapted for insertion into a PCIe expansion slot on a motherboard of the computer system for transmitting PCIe signals between the motherboard and the interface card, an interface port configured to mate with a connector of the cable, and a logic integrated circuit on the printed circuit board, the logic integrated circuit functionally connecting the edge connector with the expansion slot and amplifying and propagating clock and data PCIe signals therebetween that are compliant with a PCIe standard. The interface card and cable lacks the capability of transmitting power therethrough to a PCIe-compliant peripheral device connected to the interface card through the interface port.

Abstract: Methods of operating a non-volatile solid state memory-based mass storage device having at least one non-volatile memory component. In one aspect of the invention, the one or more memory components define a memory space partitioned into user memory and over-provisioning pools based on a P/E cycle count stored in a block information record. The storage device transfers the P/E cycle count of erased blocks to a host and the host stores the P/E cycle count in a content addressable memory. During a host write to the storage device, the host issues a low P/E cycle count number as a primary address to the content addressable memory, which returns available block addresses of blocks within the over-provisioning pool as a first dimension in a multidimensional address space. Changed files are preferably updated in append mode and the previous version can be maintained for version control.

Abstract: A memory controller and methods thereof suitable for operating a system utilizing multiple memory bus channels and/or multiple banks of memory devices on each channel wherein the memory devices is polled only when necessary. The memory controller includes means for determining a status of each individual memory device of the plurality of memory devices, a channel controller for each memory bus channel, and at least one status register on which is stored a plurality of bits. The channel controller maintains a derived status of each individual memory device based on the current and previous status data. Each individual bit of the plurality of bits of the status register corresponds to an individual memory device of the plurality of memory devices and indicates the derived status of the individual memory device which are used to determine whether to check for a queued command destined for the individual memory device.

Abstract: A solid state drive having at least one NAND flash memory component organized in blocks, pages and cells. Each cell is adapted to store at least two bits. Each block of the memory component is adapted to be dynamically configured to store at least one bit per cell using a first mode of operation and dynamically configured to store at least two bits per cell using a second mode of operation while the mass storage device is operating, wherein the first mode of operation entails programming fewer bits of a cell in fewer passes as compared to the second mode of operation.

Abstract: RAID storage systems and methods adapted to enable the use of NAND flash-based solid-state drives. The RAID storage system includes an array of solid-state drives and a controller operating to combine the solid-state drives into a logical unit. The controller utilizes data striping to form data stripe sets comprising data (stripe) blocks that are written to individual drives of the array, utilizes distributed parity to write parity data of the data stripe sets to individual drives of the array, and writes the data blocks and the parity data to different individual drives of the array. The RAID storage system detects the number of data blocks of at least one of the data stripe sets and then, depending on the number of data blocks detected, may invert bit values of the parity data or add a dummy data value of “1” to the parity value.

Abstract: A host server computer system that includes a hypervisor within a virtual space architecture running at least one virtualization, acceleration and management server and at least one virtual machine, at least one virtual disk that is read from and written to by the virtual machine, a cache agent residing in the virtual machine, wherein the cache agent intercepts read or write commands made by the virtual machine to the virtual disk, and a solid state drive. The solid state drive includes a non-volatile memory storage device, a cache device and a memory device driver providing a cache primitives application programming interface to the cache agent and a control interface to the virtualization, acceleration and management server.

Abstract: Disclosed is a memory device which receives a check command and check information from a Central Processing Unit (CPU), reads data written in a predetermined area of a memory based on the check information in response to the check command, and checks a data pattern of the data read based on the check information.

Abstract: A solid-state mass storage device for use with host computer systems, and methods of increasing the endurance of non-volatile memory components thereof that define a first non-volatile memory space. The mass storage device further has a second non-volatile memory space containing at least one non-volatile memory component having a higher write endurance than the memory components of the first non-volatile memory space. The second non-volatile memory space functions as a low-pass filter for host writes to the first non-volatile memory space to minimize read accesses to the first non-volatile memory space. Contents of the second non-volatile memory space are managed using a change counter.

Abstract: Provided is a controller for a solid state disk, to control simultaneous switching of pads. The controller for the solid state disk may control simultaneous switching of a plurality of output pads or a plurality of input pads that correspond to a plurality of channels. In particular, the controller may properly delay signals driven to the output pads or input pads, to reduce power supplied to the pads, and to prevent ground bouncing, as well as, maintain a quality of signals.

Abstract: A method and mass storage device that combine multiple solid state drives (SSDs) to a single volume. The device includes a carrier board and at least two solid state drives having power and data connections to the carrier board. The carrier board includes a circuit board functionally connected to a control logic and at least two secondary connectors that are disposed at different edges of the circuit board and functionally connected to the control logic. The solid state drives are connected to the carrier board through the secondary connectors, and each solid state drive has a power and data connector directly connected to one of the secondary connectors of the carrier board. The solid state drives are oriented substantially parallel to the carrier board and to each other.

Abstract: Architectures and methods for performing big data analytics by providing an integrated storage/processing system containing non-volatile memory devices that form a large, non-volatile memory array and a graphics processing unit (GPU) configured for general purpose (GPGPU) computing. The non-volatile memory array is directly functionally coupled (local) with the GPU and optionally mounted on the same board (on-board) as the GPU.

Abstract: A modular mass storage system and method that enables cableless mounting of ATA and/or similar high speed interface-based mass storage devices in a computer system. The system includes a printed circuit board, a system expansion slot interface on the printed circuit board and comprising power and data pins, a host bus controller on the printed circuit board and electrically connected to the system expansion slot interface, docking connectors connected with the host bus controller to receive power and exchange data therewith and adapted to electrically couple with industry-standard non-volatile memory devices without cabling therebetween, and features on the printed circuit board for securing the memory devices thereto once coupled to the docking connectors.

Abstract: A cache and disk management method is provided. In the cache and disk management method, a command to delete all valid data stored in a cache, or specific data corresponding to a part of the valid data may be transmitted to a plurality of member disks. That is, all of the valid data or the specific data may exist in the cache only, and may be deleted from the plurality of member disks. Accordingly, the plurality of member disks may secure more space, an internal copy overhead may be reduced, and more particularly, solid state disks may achieve better performance.

Abstract: Memory technology adapted to store data in a binary format. Such technology includes a semiconductor memory device having memory cells, each having a substrate and at least three graphene layers that are oriented to define a graphene stack disposed in a plane. The graphene stack of each memory cell is connected to a bit line and to a ground connection so that a conductive path is defined in the plane of the graphene stack. The in-plane conductivity of the graphene stack of each memory cell is altered during programming of the memory cell to define a binary value of bits stored in the memory cell.

Abstract: A Solid State Drive (SSD) controller is disclosed. When a data read command is transmitted by a host, the SSD controller may select a representative pointer from at least one first pointer by checking a point in time when data writing is completed in a buffer by at least one memory, read the data from the buffer by referring to a second pointer, and transmit the read data to the host, based on the representative pointer.

Abstract: A mass storage system comprising multiple memory cards, each with non-volatile memory components, a system bus interface for communicating with a system bus of a host system, and at least one ancillary interface. The ancillary interface is configured for direct communication of commands, addresses and data between the memory cards via a cross-link connector without accessing the system bus interface.

Abstract: A test-ahead feature for non-volatile memory-based mass storage devices to anticipate device failure. The test-ahead feature includes a method performed with a solid-state mass storage device having a controller, a cache memory, and at least one non-volatile memory device. At least a first block is reserved on the at least one non-volatile memory device as a wear-indicator block and a plurality of second blocks are used for data storage. Information is stored corresponding to the number of write and erase cycles encountered by the second blocks during usage of the mass storage device, and the information is accessed to perform wear leveling among the second blocks. The wear-indicator blocks are subjected to an offset number of write and erase cycles in excess of the number of write and erase cycles encountered by the second blocks, after which an integrity check of the first block is performed.

Abstract: RAID storage systems and methods adapted to enable the use of NAND flash-based solid-state drives. The RAID storage system includes an array of solid-state drives and a controller operating to combine the solid-state drives into a logical unit. The controller utilizes data striping to form data stripe sets comprising data (stripe) blocks that are written to individual drives of the array, utilizes distributed parity to write parity data of the data stripe sets to individual drives of the array, and writes the data blocks and the parity data to different individual drives of the array. The RAID storage system detects the number of data blocks of at least one of the data stripe sets and then, depending on the number of data blocks detected, may invert bit values of the parity data or add a dummy data value of “1” to the parity value.

Abstract: A mounting structure adapted for mounting an expansion card within a computer enclosure and configured to directly absorb and conduct heat from a heat source (such as an IC chip) on the card to the ambient atmosphere surrounding the enclosure. The mounting structure includes a mounting bracket, a heat sink adapted to contact a surface of the heat source on the expansion card, an extension interconnecting the heat sink and the mounting bracket, one or more features for conducting heat from the heat sink to the mounting bracket, and one or more features associated with the mounting bracket for dissipating heat from the mounting structure to the ambient atmosphere surrounding the enclosure.

Abstract: A solid-state mass storage device and method of operating the storage device to anticipate the failure of at least one memory device thereof before a write endurance limitation is reached. The method includes assigning at least a first memory block of the memory device as a wear indicator that is excluded from use as data storage, using pages of at least a set of memory blocks of the memory device for data storage, writing data to and erasing data from each memory block of the set in program/erase (P/E) cycles, performing wear leveling on the set of memory blocks, subjecting the wear indicator to more P/E cycles than the set of memory blocks, performing integrity checks of the wear indicator and monitoring its bit error rate, and taking corrective action if the bit error rate increases.