Patents Assigned to Oki Semiconductor
  • Patent number: 8604588
    Abstract: A semiconductor device including: a first resistance element formed of a first polysilicon layer that contains impurities; a second resistance element provided on a same surface as the first polysilicon layer, and formed of a second polysilicon layer that contains an equal amount of impurities to the first polysilicon layer; a first interlayer insulation film provided so as to cover the first resistance element and the second resistance element; and a first metal layer provided on the first interlayer insulation film so as to cover the second resistance element with the first interlayer insulation film disposed therebetween.
    Type: Grant
    Filed: February 22, 2011
    Date of Patent: December 10, 2013
    Assignee: Oki Semiconductor Co., Ltd.
    Inventors: Kenichiro Kusano, Junko Azami
  • Patent number: 8600078
    Abstract: An audio signal amplitude adjusting device and method that can always adjust the amplitude of an input audio signal to such a level as to be easy to hear with making it follow each shift in the level of the input audio signal, thus preventing the occurrence of the sense of aural discomfort and an interruption of a voice. The gain of a variable attenuator for adjusting the amplitude of the audio signal is controlled in various ways. When a momentary large noise sound is contained in the audio signal, the gain reduced state invoked to suppress the effect of the noise sound is detected, and thereafter if the amplitude of the audio signal has become smaller than the reference level due to the noise sound ending, the gain is increased each period that is shortest among the periods of control employed.
    Type: Grant
    Filed: June 21, 2010
    Date of Patent: December 3, 2013
    Assignee: Oki Semiconductor Co., Ltd.
    Inventor: Yoshiki Suzuki
  • Patent number: 8593179
    Abstract: An inverter of a delay circuit in a semiconductor integrated device that has a high resistance to an electrostatic discharge. The delay circuit includes at least one inverter. Each inverter has high and low potential parts. The low potential part includes a pair of FETs. A source terminal of one FET is connected to a drain terminal of the other FET at a first common node. The high potential part includes another pair of FETs, with a source terminal of one FET being connected to a drain terminal of the other FET at a second common node. A power supply potential is applied to the first common node when the inverter output becomes a high potential. A ground potential is applied to the second common node when the inverter output becomes a low potential.
    Type: Grant
    Filed: September 23, 2011
    Date of Patent: November 26, 2013
    Assignee: Oki Semiconductor Co., Ltd.
    Inventor: Takashi Tomita
  • Patent number: 8589113
    Abstract: A movement detection device that includes an acceleration detection unit, a splitting unit and a movement detection unit is provided. The acceleration detection unit detects each respective acceleration component of acting acceleration for each axis of a three-dimensional orthogonal coordinate system and outputs respective acceleration component data. The splitting unit splits the respective acceleration component data output from the acceleration detection unit into a stationary component obtained by low-pass filter processing and a movement component that is the respective acceleration component data from which the respective stationary component has been removed. The movement detection unit detects which axial direction the acceleration detection unit has moved in for each of the axes based on a movement component indicating the maximum value split by the splitting unit.
    Type: Grant
    Filed: August 23, 2010
    Date of Patent: November 19, 2013
    Assignee: Oki Semiconductor Co., Ltd.
    Inventor: Kazunori Fujiwara
  • Patent number: 8587507
    Abstract: A driving circuit includes a pair of operational amplifiers, one producing an analog voltage output of positive polarity, the other producing an analog voltage output of negative polarity. An output switching circuit interchanges these outputs between a pair of data lines. One or both of the operational amplifiers includes a parasitic diode having one terminal connected to the output terminal of the operational amplifier and another terminal normally connected to a power supply voltage of the operational amplifier. When the output of the operational amplifier is switched, a protective switching circuit temporarily disconnects the parasitic diode from the power supply of the operational amplifier and instead connects it to a power supply line carrying a voltage high enough, or low enough, to ensure that the parasitic diode is not forward biased by the existing voltage on the data line to which the output is switched.
    Type: Grant
    Filed: June 21, 2011
    Date of Patent: November 19, 2013
    Assignee: Oki Semiconductor Co., Ltd.
    Inventors: Hideaki Hasegawa, Atsushi Hirama, Koji Higuchi
  • Patent number: 8581642
    Abstract: A data transfer circuit includes primary data holding circuits that hold input data according to a first clock pulse signal and output data being held; and secondary data holding circuits that hold the output data of the primary data holding circuits according to a second clock pulse asynchronous to the first clock pulse and output data being held. Pulse signal generator generates a pulse signal synchronous with the second clock pulse signal when a pulse edge of the first clock pulse signal and a pulse edge of the second clock pulse signal occur at different timings and generates a pulse signal having the pulse edge the second clock pulse signal removed therefrom when the pulse edge of the the first clock pulse signal and the pulse edge of the the second clock pulse signal occur at the same timing. The secondary data holding circuits hold the output data of the primary data holding circuits synchronously with the pulse signal generated by the pulse signal generator.
    Type: Grant
    Filed: February 10, 2011
    Date of Patent: November 12, 2013
    Assignee: Oki Semiconductor Co., Ltd.
    Inventor: Daisuke Kadota
  • Patent number: 8558562
    Abstract: This method is applied to a dual-use jack of an electronic device. Either a headphone plug or a line output plug is inserted into the dual-use jack. The method determines the type of a plug connected to the dual-use jack when the plug is inserted into the dual-use jack. The determination is made based on a load resistance of the plug connected to the jack. The method includes feeding an electric current through the load resistance in a first direction. The method compares a voltage across the load resistance to a reference voltage and determines the type of the plug in use. The method also includes feeding an electric current through the load resistance in a second direction. This electric current can reduce or eliminate a pop-noise when the plug type is determined. The second direction is different from the first direction.
    Type: Grant
    Filed: November 5, 2010
    Date of Patent: October 15, 2013
    Assignee: Oki Semiconductor Co., Ltd.
    Inventor: Naotaka Saito
  • Patent number: 8559538
    Abstract: The Present invention provides a correlator including, a read-out processing circuit that reads out an OFDM signal in RAM as 2n?1 number of delay OFDM signals that are increased and delayed sequentially with their adjusted read-out timings. Complex conjugate circuits that outputs complex conjugates of the inputted nth to 2n?1th delay OFDM signals. Complex arithmetic circuits that perform complex multiplication to inputted original OFDM signal, the first to n?1th delay OFDM signals, and the output signals from the complex conjugate circuits. Moving average processing circuits take the moving average of the GI length, gain adjustment circuits adjust the gains, an adder circuit adds the outputs of the adjustment circuits, and a filter circuit smoothes the addition result. A control circuit variably controls the delay of the delay OFDM signals, the gains of the gain adjustment circuits, and the band characteristic of the filter circuit.
    Type: Grant
    Filed: August 15, 2011
    Date of Patent: October 15, 2013
    Assignee: Oki Semiconductor Co., Ltd.
    Inventor: Hiroji Akahori
  • Patent number: 8547082
    Abstract: An internal pulse waveform shaping circuit provided to an IC chip generates an internal pulse monitor signal that changes in a predetermined direction at a rise timing of an internal pulse signal during a period in which a first enable signal is asserted and a second enable signal is de-asserted and then continues in the changed state for a predetermined period of time or longer, and generates the internal pulse monitor signal that changes in the predetermined direction at a fall timing of the pulse signal during a period in which the first enable signal is de-asserted and the second enable signal is asserted and then continues in the changed state for the predetermined period of time or longer. The generated internal pulse monitor signal is output to a tester for detecting the pulse width of the internal pulse signal.
    Type: Grant
    Filed: January 25, 2011
    Date of Patent: October 1, 2013
    Assignee: Oki Semiconductor Co., Ltd.
    Inventor: Akihiro Hirota
  • Patent number: 8538336
    Abstract: A radio LSI device includes an interfering wave detecting circuit that receives an RSSI signal for a current transmit/receive channel. The interfering wave detecting circuit includes a field intensity determiner that determines whether or not the value of the RSSI signal is greater than a predetermined threshold value. The interfering wave detecting circuit also includes a duration counter that counts the duration of an interfering wave whose RSSI value is greater than the predetermined threshold value. The interfering wave detecting circuit also includes a duration comparator that, if the duration exceeds a duration comparative value, generates an interrupt signal. The radio LSI device changes the setting of the current transmit/receive channel in response to the interrupt signal.
    Type: Grant
    Filed: November 17, 2009
    Date of Patent: September 17, 2013
    Assignee: Oki Semiconductor Co., Ltd.
    Inventor: Takeshi Ichikawa
  • Patent number: 8525821
    Abstract: A display driving device includes an output circuit that drives display elements. The output circuit includes a bias circuit, an amplifier stage and an output stage. The bias circuit generates bias signals that include constant-current-control signals of a first bias signal and a second bias signal of the same polarity. The first and second bias signals are short circuited by a vertical line in the bias circuit and the vertical line is shielded. The amplifier stage is formed in a first well and constant-current-controlled by the first bias signal to amplify an input display signal. The output stage is formed in a second well. The first and second wells are formed separately in a semiconductor substrate. The output stage is constant-current-controlled by the second bias signal and supplies an output signal of the amplifier stage to the display element.
    Type: Grant
    Filed: July 29, 2009
    Date of Patent: September 3, 2013
    Assignee: Oki Semiconductor Co., Ltd.
    Inventor: Katsuyoshi Takahashi
  • Patent number: 8522613
    Abstract: There is provided an acceleration sensor including: a weight portion; plural fixed portions formed above a bottom plate around a periphery of the weight portion; a beam portion coupling the fixed portions and the weight portion, and holding the weight portion at a position separated from the bottom plate; a detection portion provided at the beam portion and detecting deformation of the beam portion; a frame portion provided so as to project out from the bottom plate and surround the fixed portions at a position separated from the fixed portions; and a lid portion of plate shape that seals an opening of the frame portion.
    Type: Grant
    Filed: November 9, 2010
    Date of Patent: September 3, 2013
    Assignee: Oki Semiconductor Co., Ltd.
    Inventor: Takeharu Suzuki
  • Patent number: 8519931
    Abstract: A source driver and drive control method that cancel offset voltages and enable quality display when a vertical synchronization signal is not fed to the source driver. A source driver receives a horizontal synchronization signal of an image signal, and a binary control signal which varies in two values in synchronization with the horizontal synchronization signal and in which start values of adjacent frames of the image signal are different, excluding a vertical synchronization signal of the image signal, to apply a drive voltage to source signal lines of a display panel. In the source driver, the vertical cycle of the image signal is analyzed based on the binary control signal; a pseudo vertical synchronization signal is generated based on the vertical cycle; and a cancel operation of an offset voltage component of the drive voltage is performed based on the pseudo vertical synchronization signal.
    Type: Grant
    Filed: May 28, 2009
    Date of Patent: August 27, 2013
    Assignee: Oki Semiconductor Co., Ltd.
    Inventor: Haisong Wang
  • Patent number: 8513778
    Abstract: Disclosed is a semiconductor device that is capable of preventing impurities such as moisture from being introduced into an active region at the time of dicing and at the time of bonding and that is capable of being easily miniaturized. The semiconductor device includes a cylindrical dummy wire having an opening for allowing a wire interconnecting a semiconductor element and an external connection terminal to pass therethrough, extending in an insulation film provided on a semiconductor layer having the semiconductor element to surround the semiconductor element, and disposed inside the external connection terminal.
    Type: Grant
    Filed: May 22, 2009
    Date of Patent: August 20, 2013
    Assignee: Oki Semiconductor Co., Ltd.
    Inventor: Shunichi Tokitoh
  • Patent number: 8508453
    Abstract: The present disclosure provides a display panel driving apparatus for driving a display panel including a plurality of display cells, in accordance with an inputted image signal, including, a first latch section that successively reads and holds a pixel data piece for each pixel based on the inputted image signal, a second latch section that successively reads and outputs pixel data pieces every Q pieces (Q is an integer equal to or larger than 2) with a predetermined time difference therebetween in accordance with a load signal, a drive potential generating section that generates a drive potential to drive each of the display cells based on the outputted pixel data pieces, and an output gate section that applies the drive potentials to the respective display cells of the display panel, simultaneously after an elapse of a predetermined time period from a timing of supplying the load signal.
    Type: Grant
    Filed: July 31, 2009
    Date of Patent: August 13, 2013
    Assignee: Oki Semiconductor Co., Ltd.
    Inventor: Akira Nakayama
  • Patent number: 8501542
    Abstract: A dual-face package has an LSI chip sealed with a mold resin, and electrodes for external connections on both of the front face and the back face. The LSI chip is bonded onto the die pad of a leadframe whose outer lead portions are exposed as back-face electrodes at at least the back face. The LSI chip and a plurality of inner lead portions of the leadframe are connected by wiring. At least some of the plurality of inner lead portions have front-face electrodes integrally formed by working a portion of the leadframe. Head faces of the front-face electrodes, or bump electrodes connected to the respective head faces of the front-face electrodes serve as electrodes for external connections to another substrate, element, or the like.
    Type: Grant
    Filed: March 5, 2012
    Date of Patent: August 6, 2013
    Assignee: Oki Semiconductor Co., Ltd
    Inventors: Masamichi Ishihara, Harufumi Kobayashi
  • Patent number: 8500984
    Abstract: A method for manufacturing a printed circuit board having an insulative board and a plurality of electroconductive pads arranged in a grid shape on the insulative board, the method including a step for forming an electroconductive film on the insulative board; a step for forming a pattern on the electroconductive film so as to form the electroconductive pads, a lead wire connected to at least one of the electroconductive pads, and inter-pad wiring for electrically connecting each of the electroconductive pads not connected to the lead wire to any of the electroconductive pads connected to the lead wire, the inter-pad wiring being disposed between mutually adjacent electroconductive pads; a step for plating each of the electroconductive pads by immersing the insulative board in a plating bath and energizing each of the electroconductive pads through the lead wire; and a step for removing the inter-pad wiring.
    Type: Grant
    Filed: June 24, 2009
    Date of Patent: August 6, 2013
    Assignee: Oki Semiconductor Co., Ltd.
    Inventors: Yoshimi Egawa, Harufumi Kobayashi
  • Patent number: 8495270
    Abstract: A communication interface device includes: a first interface circuit including a chip select terminal connected to a first terminal, a clock terminal connected to a second terminal, and a data terminal connected to a third terminal; and a second interface circuit including a second clock terminal connected to the first terminal and a data terminal connected to the third terminal. In a case of performing communication by the first interface circuit, a fixed signal fixed at a predetermined level is input into the first terminal, a clock signal is input into the second terminal, and a data signal is input into the third terminal, and in a case of performing communication by the second interface circuit, the clock signal is input into the first terminal and the data signal is input into the third terminal.
    Type: Grant
    Filed: June 14, 2011
    Date of Patent: July 23, 2013
    Assignee: Oki Semiconductor Co., Ltd.
    Inventor: Tsuguto Maruko
  • Publication number: 20130185575
    Abstract: A semiconductor device includes first, second and third power supply terminals respectively supplied with first, second and third power supply voltages. The semiconductor device also includes a first terminal connectable to a host device and a second terminal connectable to a peripheral device. The semiconductor device also includes a first circuit block connected to the first terminal and the first power supply terminal and receiving data output from the host device based on the first power supply voltage, a second circuit block connected to the second terminal and the third power supply terminal and receiving data output from the peripheral device based on the third power supply voltage, and a third circuit block connected to the second power supply terminal and controlling operation of the first circuit block and the second circuit block based on the second power supply voltage.
    Type: Application
    Filed: March 6, 2013
    Publication date: July 18, 2013
    Applicant: Oki Semiconductor Co., Ltd.
    Inventor: Oki Semiconductor Co., Ltd.
  • Patent number: 8486728
    Abstract: A method of manufacturing a semiconductor device and a semiconductor device including a first semiconductor element mounted on a first surface of a base plate, wherein solder balls are formed on a second opposite surface of the base plate—such that the second opposite surface includes an area without solder balls. At least one second semiconductor element is mounted to the base plate at the area of the second surface without solder balls. The at least one semiconductor element may be mounted to the base plate using low molecular adhesive, or in the alternative, high temperature solder.
    Type: Grant
    Filed: August 8, 2011
    Date of Patent: July 16, 2013
    Assignee: Oki Semiconductor Co., Ltd.
    Inventors: Shinji Ohuchi, Shigeru Yamada, Yasushi Shiraishi