Patents Assigned to Oki Semiconductor
  • Patent number: 8188555
    Abstract: A capacitive sensor includes a semiconductor substrate, a fixed electrode serving as a first electrode formed on a surface of or in the semiconductor substrate, a structure formed on the semiconductor substrate to have a vibratable second electrode that is formed to be spaced from and opposed to the semiconductor substrate and from the fixed electrode serving as the first electrode, a sealing member serving as a first sealing member formed on the semiconductor substrate to be spaced from the structure, to cover the structure, and to have a through hole serving as a first through hole, and a movable electrode serving as a vibratable third electrode formed on the sealing member to block up the through hole, and to be spaced from and opposed to the movable electrode.
    Type: Grant
    Filed: November 25, 2008
    Date of Patent: May 29, 2012
    Assignee: OKI Semiconductor Co., Ltd.
    Inventor: Yasushi Igarashi
  • Patent number: 8188580
    Abstract: A semiconductor device, a semiconductor element, and a substrate are provided, which allow the semiconductor element to be provided with a reduced size when combined. The semiconductor device has a rectangular semiconductor element mounted on a substrate formed with an external input terminal, an external output terminal, and a plurality of wiring patterns connected to each of the external input terminal and the external output terminal. The semiconductor element includes a grayscale voltage generating unit for generating a plurality of grayscale voltages by dividing a reference voltage, a plurality of electrodes for the reference voltage formed in the neighborhood of the grayscale voltage generating unit; and an internal wiring for connecting the grayscale voltage generating unit and the reference voltage electrodes. The substrate includes a wiring pattern for the reference voltage for connecting the external input terminal and the reference voltage electrodes.
    Type: Grant
    Filed: December 29, 2010
    Date of Patent: May 29, 2012
    Assignee: Oki Semiconductor Co., Ltd.
    Inventor: Akira Nakayama
  • Patent number: 8183643
    Abstract: A semiconductor device includes diffusion layers formed in a SOI layer under a side-wall, a channel formed between the diffusion layers, silicide layers sandwiching the diffusion layers wherein interface junctions between the diffusion layers and the silicide layers are (111) silicon planes.
    Type: Grant
    Filed: September 26, 2001
    Date of Patent: May 22, 2012
    Assignee: Oki Semiconductor Co., Ltd.
    Inventors: Takashi Ichimori, Norio Hirashita
  • Patent number: 8183637
    Abstract: There is provided a semiconductor device including: a field effect transistor that is provided with a gate region, a drain region and a source region and that is formed on a substrate; a circuit region that is formed on the substrate so as to be electrically isolated from the field effect transistor; a first guard ring that is formed in a ring shape encircling the field effect transistor and that includes an internal resistance; and a second guard ring that is formed in a ring shape encircling the circuit region, that forms a capacitance between the second guard ring and the gate region by capacitive coupling with the gate region, and that includes an internal resistance.
    Type: Grant
    Filed: January 26, 2010
    Date of Patent: May 22, 2012
    Assignee: Oki Semiconductor Co., Ltd.
    Inventor: Chikashi Fuchigami
  • Patent number: 8183147
    Abstract: A method of fabricating a semiconductor device includes: forming a semiconductor chip portion having an electrode on a main surface of a wafer; forming a first resist pattern having a first opening on the electrode; filling the first opening with a first electrically conductive material, thereby forming an electrically conductive post; removing the first resist pattern after said forming of the electrically conductive post; forming an interlayer dielectric film having a second opening positioned on the electrically conductive post; and forming an electrically conductive redistribution layer extending from an upper surface of the electrically conductive post over an upper surface of the interlayer dielectric film.
    Type: Grant
    Filed: February 14, 2011
    Date of Patent: May 22, 2012
    Assignee: Oki Semiconductor Co., Ltd.
    Inventor: Osamu Koike
  • Patent number: 8178421
    Abstract: A method of manufacturing a semiconductor device capable of preventing a cut portion from becoming chipped when dicing. The method of manufacturing a semiconductor device includes preparing a semiconductor wafer having an upper surface (first surface) including a plurality of device regions and partition regions for dividing the plurality of device regions, and a lower surface (second surface) opposite from the upper surface (first surface), forming upper layer wires on the device regions of the upper surface (first surface), etching the semiconductor wafer from a side of the lower surface (second surface) to form a through hole through which the upper layer wire is exposed, and to form a groove in a region of the lower surface (second surface) corresponding to the partition region of the upper surface (first surface), and dicing the semiconductor wafer to form individual device regions.
    Type: Grant
    Filed: September 6, 2007
    Date of Patent: May 15, 2012
    Assignee: Oki Semiconductor Co., Ltd.
    Inventor: Hidekazu Kikuchi
  • Patent number: 8178904
    Abstract: A gate array of a semiconductor substrate on which plural unit cells are arranged in parallel, the unit cells having the same pattern that includes a source potential region VDD, a PMOS, an NMOS and a ground potential region GND. Metal wiring lines being formed, with an insulating layer between, on the unit cells, with contacts that make electrical connection between the metal wiring lines and the unit cell transistors. The gate wiring of a transistor in a non-used unit cell is used in place of a metal wiring line. By doing so, the area of metal wiring lines in a gate array is reduced and the array wiring efficiency is increased.
    Type: Grant
    Filed: December 10, 2010
    Date of Patent: May 15, 2012
    Assignee: Oki Semiconductor Co., Ltd.
    Inventor: Hirofumi Uchida
  • Patent number: 8179738
    Abstract: An internal power supply control circuit of a semiconductor memory includes a periodic signal generating unit that generates a periodic signal to generate a permission signal to intermittently permit supply of power from an internal power supply circuit of the semiconductor memory to an internal circuit thereof with a predetermined period, when a mode changes from a normal operation mode where power is always supplied from the internal power supply circuit to the internal circuit to a standby mode where consumption power is further suppressed as compared with consumption power in the normal operation mode, and a permission signal output unit that outputs the permission signal synchronized with the periodic signal to the internal power supply circuit, when a mode signal indicating any mode of the normal operation mode and the standby mode and the periodic signal are input and the input mode signal indicates the standby mode.
    Type: Grant
    Filed: March 22, 2010
    Date of Patent: May 15, 2012
    Assignee: Oki Semiconductor Co., Ltd.
    Inventor: Akihiro Hirota
  • Patent number: 8169429
    Abstract: The object of the present invention is reducing power consumption of a driving power supply circuit. In the case where the driving voltage Vi is higher than the reference voltage ViH, The signal S3P, S3N of the differential amplifier 30P, 30N become level “L” concurrently, and the signal S4P, S4N of the output circuit 40P, 40N become level “H”. Subsequently, the NMOS 62 becomes on-state and decreases the driving voltage Vi of the node N6. At the above stage, the control signal CP becomes level “L”, then the operation of the constant current circuit 20P is halted.
    Type: Grant
    Filed: September 2, 2010
    Date of Patent: May 1, 2012
    Assignee: Oki Semiconductor Co., Ltd.
    Inventor: Hijiri Shirasaki
  • Patent number: 8164164
    Abstract: A semiconductor wafer has a substrate, and a plurality of active areas formed on the substrate. Integrated circuits are formed in the active areas. The semiconductor wafer also has dicing areas formed between the adjacent active areas. A seal ring is formed along the edge (periphery) of each active area. The semiconductor wafer also has interconnects formed closely to the inside of the seal ring. A protective layer covers the active areas. A protective film is formed on the protective layer at the locations of the active areas. The semiconductor wafer also has other interconnects formed on the protective film for electrical connection to the integrated circuits. Preferably, when the aspect ratio of a groove formed in the protective layer between the seal ring and the interconnect is 0.5 or more, this groove is covered with the protective film.
    Type: Grant
    Filed: September 22, 2010
    Date of Patent: April 24, 2012
    Assignee: Oki Semiconductor Co., Ltd.
    Inventor: Takashi Ohsumi
  • Patent number: 8166089
    Abstract: A sampled data averaging circuit which comprises sampling means for sampling input data at predetermined timing by a number of sampling times set, division means for dividing the sampled data by the number of sampling times for each time the input data is sampled, and accumulation means for sequentially accumulating the division result, and an average value is obtained from the accumulation result of the accumulation means.
    Type: Grant
    Filed: July 26, 2007
    Date of Patent: April 24, 2012
    Assignee: Oki Semiconductor Co., Ltd.
    Inventor: Masahiko Ohkubo
  • Patent number: 8164376
    Abstract: A clock frequency diffusing device including a multiphase clock signal generator, a random number generator, signal selectors, and a clock signal generator. The multiphase clock signal generator receives an input clock signal and produces a plurality of delayed clock signals that are delayed relative to the input clock signal by various amounts of time. The clock signal selector randomly chooses one of the delayed signals based upon random numbers generated by the random number generator and produces a selector output signal based on its chosen delayed clock signal. A clock signal generator receives the selector output signal and produces an output clock signal.
    Type: Grant
    Filed: February 19, 2008
    Date of Patent: April 24, 2012
    Assignee: Oki Semiconductor Co., Ltd.
    Inventor: Shuji Furichi
  • Patent number: 8164168
    Abstract: A semiconductor package including a semiconductor chip; a base member on which the semiconductor chip is mounted; a plurality of leads formed on the base member, the leads including inner ends electrically connected to the semiconductor chip and outer ends; and an index for identifying locations of specific leads.
    Type: Grant
    Filed: June 30, 2006
    Date of Patent: April 24, 2012
    Assignee: Oki Semiconductor Co., Ltd.
    Inventor: Tae Yamane
  • Publication number: 20120092938
    Abstract: Semiconductor memory including a reference amplifier and a high-speed start-up circuit having four FETs. The reference amplifier supplies the reference voltage to a sense amplifier via a reference voltage supply line. The high-speed startup circuit has four FETs. The first FET is turned on to apply a first voltage onto a first line when the enable signal indicates deactivation. The second FET is turned on to apply ground potential onto the first line when the voltage on the reference voltage supply line is higher than a gate threshold voltage value. The third FET is turned on to generate the first voltage when the enable signal indicates activation. The fourth FET is turned off when the first line is at ground potential and is turned on to supply the first voltage from the third FET onto the reference voltage supply line when the first voltage is applied onto the first line.
    Type: Application
    Filed: September 20, 2011
    Publication date: April 19, 2012
    Applicant: OKI SEMICONDUCTOR CO., LTD.
    Inventor: Akira AKAHORI
  • Patent number: 8160523
    Abstract: A channel detecting method executes a process for instructing a broadcast wave scan start, a process for performing tuning control, a process for starting initialization/operation of an OFDM demodulation section and starting the counting of a synchronous establishment timer unit, a process for determining that broadcasting is being conducted, a process for determining the expiration of the synchronous establishment timer unit, a process for outputting a TS signal and notifying that a broadcast parameter is being detected, a process for instructing transition to the next channel, a process for making a decision as to a final channel, a process for performing a transition operation, and a process for terminating a broadcast wave scan. When no broadcast is being conducted, a demodulation unit, an error correction unit and a decoder are not operated.
    Type: Grant
    Filed: October 16, 2007
    Date of Patent: April 17, 2012
    Assignee: Oki Semiconductor Co., Ltd.
    Inventor: Shigeru Amano
  • Patent number: 8159509
    Abstract: A color display device has a display screen having pixels arrayed, each of which is composed of primary color sub-pixels capable of reproducing respective primary colors and at least one subsidiary color sub-pixel capable of reproducing gray. While gradation signals are generated and supplied to the primary color sub-pixels on the basis of the primary color components of an image to be displayed, the gradation signal to be supplied to the subsidiary color sub-pixel is generated on the basis of the intensity component of the image. The color display device is attained in which the number of gradation levels can be substantially increased without increasing the number of gradation levels of the primary colors.
    Type: Grant
    Filed: March 28, 2008
    Date of Patent: April 17, 2012
    Assignee: Oki Semiconductor Co., Ltd.
    Inventor: Hideki Kanou
  • Publication number: 20120086697
    Abstract: There is provided a driving device of a display device, including: a first switching portion; a second switching portion; and a control section that, when the potential of a drive signal line is lower than a target potential, operates the first switching portion by using, as a first reference potential, a potential that is less than or equal to the target potential and that is closest to the target potential, among predetermined n types (n?1) of potentials, and, when the potential of the drive signal line is higher than the target potential, operates the second switching portion by using, as a second reference potential, a potential that is greater than or equal to the target potential and that is closest to the target potential, among the n types of potentials.
    Type: Application
    Filed: September 30, 2011
    Publication date: April 12, 2012
    Applicant: OKI SEMICONDUCTOR CO., LTD.
    Inventors: Hideaki Hasegawa, Hiroyoshi Ichikura, Kazuhide Aoyama
  • Patent number: 8154070
    Abstract: A nonvolatile memory includes a semiconductor substrate having a body member and a step member formed on the body member, a highly doped first well layer formed on the step member, a control electrode formed on the step member, a first and a second diffusion layers in the substrate, lightly doped second well layers formed on the main surface of the substrate between the first or the second diffusion layer and the first well layer, and a first and a second charge-storage multi-layers sandwiching the step member and the control electrode, each of the first and the second charge-storage multi-layers including a bottom oxide layer, a charge-storage film, a top oxide layer and a floating electrode which are formed in that order.
    Type: Grant
    Filed: December 5, 2007
    Date of Patent: April 10, 2012
    Assignee: Oki Semiconductor Co., Ltd.
    Inventor: Toshikazu Mizukoshi
  • Patent number: 8154944
    Abstract: Disclosed herein is a semiconductor memory device which prevents the voltage of a select bit line from being reduced due to the action of coupling capacitance between the select bit line and a non-select bit line, reduces current consumption, and enables high speed reading of bit lines. The semiconductor memory device includes a plurality of memory banks, a plurality of second bit lines, a plurality of selector circuits, a voltage supply circuit. Each of the memory banks includes a plurality of first bit lines, a plurality of word lines, and a plurality of memory banks which are installed between the first bit lines and the word lines. The voltage supply circuit holds non-select bit lines of the first bit lines at the GND level at all times.
    Type: Grant
    Filed: December 3, 2009
    Date of Patent: April 10, 2012
    Assignee: Oki Semiconductor Co., Ltd.
    Inventor: Takeo Takahashi
  • Patent number: 8154132
    Abstract: A semiconductor device of the invention include a rectangular semiconductor element mounted on a substrate formed with an external input terminal, an external output terminal, and a plurality of wiring patterns connected to each of the external input terminal and the external output terminal. The semiconductor element comprises, a plurality of first electrodes formed along a first edge of a surface thereof, a plurality of second electrodes formed along an edge opposite to the first edge of the surface, a plurality of third electrodes formed in the neighborhood of a functional block, and an internal wiring for connecting the first electrodes and the third electrodes. The substrate comprises, a first wiring pattern for connecting the external input terminal and the first electrodes, a second wiring pattern for connecting the external output terminal and the second electrodes, and a third wiring pattern for connecting the first electrodes and the third electrodes.
    Type: Grant
    Filed: March 17, 2008
    Date of Patent: April 10, 2012
    Assignee: Oki Semiconductor Co., Ltd.
    Inventor: Akira Nakayama