Abstract: A system for masking bits in a configuration. The system has a bus with first and second sets of bit lines. A line from the first set is paired with aline from the second set; the paried lines are coupled to each cell in the configuration register. A logic circuit is connected to each register cell and the corresponding paired lines. Depending upon the state of the bit signal of the second set bit line, the logic circuit passes the bit signal on the first set bit line for loading into the register cell or reloads the bit line signal already in the register cell. In this manner, masking operations in the configuration register can be performed very quickly.

Abstract: A printed cirucit board design capable of accepting both first and second versions of an IC device. First and second IC devices (10, 20) have pins disposed along respective first and second rectangular peripheries (12a-b and 15a-b; 22a-b and 23a-b). Each pin on the first IC devices has a functional counterpart pin on the second IC device. The board configuration contains pads in first and second arrays (32a-b and 35a-b; 32a, 32c, 33a-b) that correspond to the pins on the first and second IC devices. At least some of the pads (32b) of the first array do not physically conicide with pads in the second array and are located within the rectangle defined by the second array. Each non-overlapping pad in the first array is connected by a circuit board trace (40) to a respective pad in the second array such that each circuit board trace joins two pads corresponding to counterpart pins.

Abstract: A technique for providing external mode select information to a chip capable of operating in different modes without adding pin overhead. One of the normal signal pins of the chip is used as an input pin for a brief period of time at power-on before the chip becomes fully operational. During this time, a mode select signal from outside is communicated onto the pin and latched into the chip, where it remains during subsequent normal operation of the chip.

Abstract: A method and apparatus for scaling interlaced video data allows the video data to be scaled to any desired size, either larger or smaller than the original image. The method considers each line of input data in each field sequentially, and determines whether the line is to be saved and whether the data lines in each successive field will also be saved, discarded, or duplicated, saving space in the output buffer for the saved and duplicated data lines to come as necessary. The method can accommodate interlaced data with N field and a scaling factor M. An apparatus for implementing the method for two header fields and scaling factor N is also described.

Abstract: A method and apparatus for suspending the operation of a computer at any desired point and resuming operation at exactly the same point is disclosed. At the point where suspension is chosen, the current state of the computer is stored in the computer's Random Access Memory and power is disconnected to all other components in the computer. When resumption of operation is commanded, power is restored to all components and the current computer state is retrieved from the Random Access Memory and restored, allowing operations to continue from exactly the same point as they were suspended. The invention encourages turning off the computer for even brief periods of non-use, as there is almost no waiting time when resumption of operation is commanded.

Abstract: A data processing system includes a video controller and a flat panel display system. The flat panel display system includes first and second flat panel displays adapted so as to appear to be essentially a single display. The video controller includes a first and second address generator for generating first and second address information and a counter for counting vertical sync position to identify alternating first and second display frames. The controller outputs the first address information to drive the first display and the second address information to drive the second display during the first display frames and outputs the second address information to drive the first display and the first address information to drive the second display during the second display frames. The displays are identical and the address generators are identical. The use of dual displays with dual, flip-flopping address generators is more advantageous than using a single address generator to drive two display panels.

Abstract: An improved memory controller which can support varying numbers of banks of memory without requiring any more RAS output pins than are necessary for a minimum number of banks of memory. The memory controller chip has N RAS output pins. An internal decoder selects one of N decode outputs after decoding internally provided coded RAS addresses. A timing signal is generated to control the duration of the selected decoder output to provide the proper pulse length for the RAS signal. An internal multiplexer, with its outputs coupled to the RAS output pins, selects either the N decode outputs from the decoder or the timing signal and the internally provided addresses directly.

Abstract: An integrated circuit chip that facilitates connecting peripheral devices to an MCA Micro Channel Architecture bus system. With the present invention manufacturers of adapter boards and cards can easily interface peripheral devices to an MCA bus. With the present invention the MCA interface is segmented in a different manner than it is segmented in prior art adapters. In the approach utilized with the present invention the interface has been partitioned so that the microchannel signals and the protocol signals common to all functions are contained on an interface chip.

Abstract: A memory controller which can map expanded memory space (EMS) addresses into the dynamic random access memory (DRAM) behind video random access memory (RAM) addresses or other reserved areas of memory. A single chip has both a DRAM decoder and an EMS decoder operating in parallel. A DRAM decoder examines received addresses and provides an enable signal to a DRAM timing circuit if the address is within the DRAM range and not for a reserved group of addresses. A separate EMS decoder provides a translated address when a received address is within an EMS window. The EMS decoder also provides an EMS timing signal to the DRAM timing circuit.

Abstract: The present invention provides a fast bit blitter method and circuit which uses less logic than do prior art bit blitter circuits. A circuit built in accordance with the present invention includes four main components each of which only has as many bit positions as does the data bytes that are being shifted. The four main components are a storage register, a multiplexer bank, a multiplexer selector and a barrel shifter. As data words are serially read out of memory, they are temporarily stored in the register. The multiplexer gates selected bit from the word stored in the register, together with selected bits from the next word that appears on the data bus to the barrel shifter. The barrel shifter does the appropriate shifting. Alternatively, the barrel shifter can be located before the multiplexer in the data path.

Abstract: The present invention provides a memory organization scheme for a high-performance memory controller. The memory organization of the present invention combines page mode techniques and interleaving techniques to achieve high-performance.Sequential pages of memory are interleaved between memory banks so that memory accesses which are a page apart will be to two different memory banks. A page is preferably defined by a single row, with 2K columns per row defining the number of bits in a page. Accesses to bits in the same page as a previous access omit the row pre-charge cycle, thus speeding up the memory cycle. Accesses to a separate bank of memory chips from the previous access are likewise speeded up since there is no need to wait for the completion of the cycle in the previous bank before initiating the cycle in the separate bank.

Abstract: A video graphics controller circuit for a personal computers includes a standard, EGA-compatible graphics adapter and a high-resolution companion module. A method is disclosed for configuring the graphics adapter is to generate 2 pixels in parallel in each clock cycle. The companion module serializes the pixels to generate a serial stream of pixels at twice the frequency of the graphics adapter. The companion module can also be configured as a video line driver so that the graphics controller circuit can also run software in standard video modes.

Abstract: The present invention provides a memory addressing system that can accommodate multiple size DRAMS. DRAMS of various sizes can be mixed in a variety of ways. The present invention provides a hardware register associated with each pair of banks of DRAMS. This hardware register is programmable to indicate the type of DRAMS that have been inserted in the particular memory banks and to indicate the starting address of the particular set of memory banks. Using this technique, it is not necessary to insert the largest memory chips in the first memory bank. Memory chips of either size can be inserted in either set of memory banks and the information in the programmable register is used to control circuitry which appropriately modifies the accessing signals which are sent to the memory system.