Patents Assigned to ON Semiconductor
  • Publication number: 20200402968
    Abstract: A semiconductor device includes first cell rows and second cell rows. The first cell rows extend in a first direction. Each of the first cell rows has a first row height. The second cell rows extend in the first direction. Each of the second cell rows has a second row height. The first row height is greater than the second row height. The first cell rows and the second cell rows are interlaced in a periodic sequence. A first row quantity of the first cell rows in the periodic sequence is greater than a second row quantity of the second cell rows in the periodic sequence.
    Type: Application
    Filed: April 22, 2020
    Publication date: December 24, 2020
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Hui-Zhong ZHUANG, Xiang-Dong CHEN, Lee-Chung LU, Tzu-Ying LIN, Yung-Chin HOU
  • Publication number: 20200400793
    Abstract: A time-of-flight ranging device suitable for indirect time-of-flight ranging is provided. The time-of-flight ranging device includes a light emitting module, a first sensing pixel, a second sensing pixel, a differential readout circuit, and a processing circuit. The light emitting module emits a light pulse to a sensing target, so that the sensing target reflects a reflected light pulse. The first sensing pixel generates a first sensing signal and a second sensing signal. The second sensing pixel generates a third sensing signal and a fourth sensing signal. The differential readout circuit generates first digital data according to the first sensing signal and the third sensing signal and generates second digital data according to the second sensing signal and the fourth sensing signal. The processing circuit calculates a distance between the time-of-flight ranging device and the sensing target according to the first digital data and the second digital data.
    Type: Application
    Filed: June 19, 2020
    Publication date: December 24, 2020
    Applicant: Guangzhou Tyrafos Semiconductor Technologies Co., LTD
    Inventors: Ping-Hung Yin, Jia-Shyang Wang
  • Publication number: 20200402914
    Abstract: A method for forming a semiconductor device structure is provided. The method includes forming a first mask layer over a dielectric layer. The first mask layer has a first trench, and the first trench has a first inner wall and a bottom surface. The method includes forming an anti-bombardment layer over a first top surface of the first mask layer. The method includes forming a second mask layer over the first inner wall of the first trench. The method includes removing the first portion, the first mask layer, the anti-bombardment layer, and the second mask layer to form a third trench in the dielectric layer. The method includes forming a conductive structure in the third trench.
    Type: Application
    Filed: September 2, 2020
    Publication date: December 24, 2020
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chi-Cherng JENG, Shyh-Wei CHENG, Yun CHANG, Chen-Chieh CHIANG, Jung-Chi JENG
  • Publication number: 20200403094
    Abstract: A semiconductor device includes a semiconductor substrate, a gate stack, an air spacer, a first spacer, a second spacer, a sacrificial layer, and a contact plug. The gate stack is on the semiconductor substrate. The air spacer is around the gate stack. The first spacer is around the air spacer. The second spacer is on the air spacer and the first spacer. The sacrificial layer is on the gate stack, and an etching selectivity between the second spacer and the sacrificial layer is in a range from about 10 to about 30. The contact plug lands on the second spacer and the gate stack.
    Type: Application
    Filed: November 20, 2019
    Publication date: December 24, 2020
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Jia-Chuan YOU, Chia-Hao CHANG, Tien-Lu LIN, Yu-Ming LIN, Chih-Hao WANG
  • Publication number: 20200402812
    Abstract: A semiconductor device includes a substrate, a first well, a second well, a metal gate, a poly gate, a source region, and a drain region. The first well and the second well are within the substrate. The metal gate is partially over the first well. The poly gate is over the second well. The poly gate is separated from the metal gate, and a width ratio of the poly gate to the metal gate is in a range from about 0.1 to about 0.2. The source region and the drain region are respectively within the first well and the second well.
    Type: Application
    Filed: February 20, 2020
    Publication date: December 24, 2020
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Alexander KALNITSKY, Wei-Cheng WU, Harry-Hak-Lay CHUANG
  • Publication number: 20200402942
    Abstract: A semiconductor structure includes a first semiconductor device, a second semiconductor device, a connection device and a redistribution circuit structure. The first semiconductor device is bonded on the second semiconductor device. The connection device is bonded on the second semiconductor device and arranged aside of the first semiconductor device, wherein the connection device includes a first substrate and conductive vias penetrating through the first substrate and electrically connected to the second semiconductor device. The redistribution circuit structure is located over the second semiconductor device, wherein the first semiconductor device and the connection device are located between the redistribution circuit structure and the second semiconductor device. The redistribution circuit structure and the first semiconductor device are electrically connected to the second semiconductor device through the conductive vias of the connection device.
    Type: Application
    Filed: April 8, 2020
    Publication date: December 24, 2020
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Ming-Fa Chen, Sung-Feng Yeh, Tzuan-Horng Liu, Chao-Wen Shih
  • Publication number: 20200400796
    Abstract: A time of flight device and a time of flight method are provided. The time of flight device includes a first time-to-digital converter, a second time-to-digital converter, a driving circuit, a sensing light source, a sensing pixel and a processing circuit. The driving circuit provides a pulse signal and a reference pulse signal simultaneously. The first time-to-digital converter determines first depth data based on the reference pulse signal. The sensing light source emits a light pulse to a sensing object based on the pulse signal. The sensing pixel receives a reflected light pulse reflected by the sensing object and outputs a reflected pulse signal to the second time-to-digital converter so that the second time-to-digital converter determines second depth data based on the reflected pulse signal. The processing circuit subtracts the first depth data from the second depth data to obtain real depth data.
    Type: Application
    Filed: June 10, 2020
    Publication date: December 24, 2020
    Applicant: Guangzhou Tyrafos Semiconductor Technologies Co., LTD
    Inventors: Ping-Hung Yin, Jia-Shyang Wang
  • Publication number: 20200400726
    Abstract: Implementations of voltage sensing systems may include: a high side current mirror coupled to a reference current source coupled to at least one diode. The at least one diode may be coupled to a resistor and to a comparator. The resistor may be coupled to the ground. The comparator may be coupled with a reference voltage. The comparator may be configured to receive a comparison voltage from the diode and output whether the comparison voltage is higher or lower than the reference voltage.
    Type: Application
    Filed: August 31, 2020
    Publication date: December 24, 2020
    Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Catalin Ionut Petroianu, Alexandra-Oana Petroianu, Pavel Londak
  • Publication number: 20200403587
    Abstract: Various embodiments of the present technology may provide methods and apparatus for an amplifier integrated circuit. The amplifier integrated circuit may provide two amplifiers, one amplifier set to a low gain bandwidth product to amplify at a higher speed and the other amplifier set to a high gain bandwidth product to amplify at a lower speed. The amplifier integrated circuit may further provide a switching circuit connected to the amplifiers, wherein the switching circuit is responsive to a control signal and operates to selectively activate the high speed amplifier and the low speed amplifier in sequence.
    Type: Application
    Filed: June 20, 2019
    Publication date: December 24, 2020
    Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventor: Tsutomu MURATA
  • Publication number: 20200402958
    Abstract: A semiconductor device package includes a redistribution layer, a first semiconductor device, a second semiconductor device, a first insulation body, and a second insulation body. The first semiconductor device can be disposed on the redistribution layer. The second semiconductor device can be stacked on the first semiconductor device. The first insulation body can be disposed between the first semiconductor device and the second semiconductor device. The first insulation body may have a number of first particles. The second insulation body can encapsulate the first insulation body and have a number of second particles. One of the number of first particles can have a flat surface.
    Type: Application
    Filed: June 20, 2019
    Publication date: December 24, 2020
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Hsu-Nan FANG, Chen Yuan WENG
  • Publication number: 20200402897
    Abstract: A semiconductor device package includes a first substrate, a second substrate, a conductive structure, a first solder and a second solder. The second substrate is disposed over the first substrate. The conductive structure is disposed between the first substrate and the second substrate. The conductive structure includes a first wetting portion, a second wetting portion, and a non-wetting portion disposed between the first wetting portion and the second wetting portion. The first solder covers the first wetting portion and connects the conductive structure to the first substrate. The second solder covers the second wetting portion and connects the conductive structure to the second substrate. The first solder is spaced apart from the second solder by the non-wetting portion.
    Type: Application
    Filed: June 19, 2019
    Publication date: December 24, 2020
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventor: Chang-Lin YEH
  • Publication number: 20200403501
    Abstract: A charge-pump boosting is provided. A first resistor is connected to a first storage capacitor and receives a reference voltage, and a second resistor is connected to a second storage capacitor and receives the reference voltage. A first rectifying device is connected to the first storage capacitor and a voltage output. A first clock signal and the reference voltage are used to charge the first storage capacitor, and the first clock signal is used to selectively turn on the first rectifying device to charge the voltage output by the first storage capacitor. The second rectifying device is connected to the second storage capacitor and the voltage output. A second clock signal and the reference voltage are used to charge the second storage capacitor, and the second clock signal is used to selectively turn on the second rectifying device to charge the voltage output by the second storage capacitor.
    Type: Application
    Filed: September 24, 2019
    Publication date: December 24, 2020
    Applicant: REALTEK SEMICONDUCTOR CORP.
    Inventors: Chien-Ming Wu, Shih-Hsiung Huang, Liang-Huan Lei
  • Publication number: 20200403090
    Abstract: A semiconductor structure includes a substrate having an active region and an isolation region, an insulating layer disposed on the substrate, a seed layer disposed on the insulating layer, a compound semiconductor layer disposed on the seed layer, a gate structure in the active region disposed on the compound semiconductor layer, an isolation structure in the isolation region disposed on the substrate, a pair of through-substrate vias in the isolation region disposed on the opposite sides of the gate structure, and a source structure and a drain structure disposed on the substrate and on the opposite sides of the gate structure. The pair of through-substrate vias pass through the isolation structure and contact the seed layer. The source structure and the drain structure electrically connect the seed layer by the pair of through-substrate vias.
    Type: Application
    Filed: June 19, 2019
    Publication date: December 24, 2020
    Applicant: Vanguard International Semiconductor Corporation
    Inventors: Shin-Cheng LIN, Wen-Hsin LIN, Marojahan TAMPUBOLON
  • Publication number: 20200404416
    Abstract: A method, comprising: obtain one or more accelerometer signals derived from an accelerometer; and determining one or more parameters of wind at the accelerometer based on the one or more accelerometer signals.
    Type: Application
    Filed: August 14, 2020
    Publication date: December 24, 2020
    Applicant: Cirrus Logic International Semiconductor Ltd.
    Inventors: Vitaliy SAPOZHNYKOV, Thomas I. HARVEY, Hock LIM, David WATTS
  • Publication number: 20200400819
    Abstract: Time of flight device and method are provided. A light-emitting module emits a first light pulse to a sensing target, and a sensing unit receives and integrates a first reflected light pulse of the sensing target. A processing circuit reads an image parameter of the sensing target through a readout circuit. The light-emitting module emits a second light pulse to the sensing target, and the sensing unit receives a second reflected light pulse of the sensing target. The processing circuit obtains a distance parameter between the sensing target and the time of flight device according to a time when the readout circuit reads the second reflected light pulse of the sensing unit. The processing circuit obtains a reflectivity of the sensing target according to the image parameter and a look-up table, and obtains a corrected distance parameter of the sensing target by correcting the distance parameter according to the reflectivity.
    Type: Application
    Filed: June 10, 2020
    Publication date: December 24, 2020
    Applicant: Guangzhou Tyrafos Semiconductor Technologies Co., LTD
    Inventors: Ping-Hung Yin, Jia-Shyang Wang
  • Publication number: 20200401189
    Abstract: An electronic device is provided, including: a display screen provided with a first surface and a second surface arranged oppositely, the display screen including: a primary display screen comprising a first portion disposed on the first surface and a second portion extending from a portion connected to the first portion to the second surface, wherein the second portion is connected to a portion of the first portion; and a secondary display screen connected to a remaining portion of the first portion, the secondary display screen being bent from a first surface of the portion connected to the first portion to the second surface.
    Type: Application
    Filed: March 12, 2019
    Publication date: December 24, 2020
    Applicant: WUHAN CHINA STAR OPTOELECTRONICS SEMICONDUCTOR DISPLAY TECHNOLOGY CO., LTD.
    Inventor: Min ZHENG
  • Publication number: 20200403588
    Abstract: A system may include a charge pump configured to boost an input voltage of the charge pump to an output voltage greater than the input voltage, a current mode control loop for current mode control of a power amplifier powered by the output voltage of the charge pump, and a controller configured to, in a current-limiting mode of the controller, control an output power of the charge pump to ensure that an input current of the charge pump is maintained below a current limit, control the power amplifier by placing the power amplifier into a high-impedance mode during the current-limiting mode, and control state variables of a loop filter of the current mode control loop during the current-limiting mode.
    Type: Application
    Filed: September 4, 2020
    Publication date: December 24, 2020
    Applicant: Cirrus Logic International Semiconductor Ltd.
    Inventors: Eric J. KING, Emmanuel MARCHAIS
  • Publication number: 20200402828
    Abstract: A scanner includes a light source configured to apply a light to a backside of a wafer. The light is reflected from the backside of the wafer. A first mirror is configured to receive the light from the backside of the wafer and reflect the light. A sensor is configured to receive the light from the first mirror and generate an output signal indicative of a backside topography of the wafer.
    Type: Application
    Filed: September 8, 2020
    Publication date: December 24, 2020
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Cheng-Mu Lin, Chi-Hung Liao, Yi-Ming Dai, Yueh Lin Yang
  • Publication number: 20200402803
    Abstract: A semiconductor device includes a semiconductor fin, a gate structure, a source epitaxy structure and a drain epitaxy structure. The semiconductor fin extends along a first direction above a substrate. The gate structure extends across the semiconductor fin along a second direction different from the first direction. The gate structure includes a gate dielectric layer wrapping around the semiconductor fin and a chlorine-containing N-work function metal layer wrapping around the gate dielectric layer. The source epitaxy structure and the drain epitaxy structure are on opposite sides of the gate structure, respectively.
    Type: Application
    Filed: September 4, 2020
    Publication date: December 24, 2020
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Li-Jung LIU, Chun-Sheng LIANG, Shu-Hui WANG
  • Publication number: 20200402960
    Abstract: A semiconductor structure includes a stacked structure. The stacked structure includes a first semiconductor die and a second semiconductor die. The first semiconductor die includes a first semiconductor substrate having a first active surface and a first back surface opposite to the first active surface. The second semiconductor die is over the first semiconductor die, and includes a second semiconductor substrate having a second active surface and a second back surface opposite to the second active surface. The second semiconductor die is bonded to the first semiconductor die through joining the second active surface to the first back surface at a first hybrid bonding interface along a vertical direction. Along a lateral direction, a first dimension of the first semiconductor die is greater than a second dimension of the second semiconductor die.
    Type: Application
    Filed: January 8, 2020
    Publication date: December 24, 2020
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Ming-Fa Chen, Chao-Wen Shih, Min-Chien Hsiao, Sung-Feng Yeh, Tzuan-Horng Liu, Chuan-An Cheng