Abstract: A semiconductor structure and a method for fabricating the semiconductor structure are provided. The method includes providing a semiconductor substrate including a dense region and a sparse region. The method also includes forming initial fins equally spaced apart from one another on the semiconductor substrate, the initial fins including a plurality of intrinsic fins and dummy fins. The intrinsic fins on the dense region has a spatial density greater than the intrinsic fins on the sparse region. In addition, the method includes forming a first isolation layer on the semiconductor substrate. The first isolation layer covers a portion of sidewalls of the dummy fins and a portion of sidewalls of the intrinsic fins. Further, the method includes forming first trenches in the first isolation layer by removing the dummy fins, and forming a second isolation layer in the first trenches.

Abstract: An integrated fan out package on package architecture is utilized along with de-wetting structures in order to reduce or eliminated delamination from through vias. In embodiments the de-wetting structures are titanium rings formed by applying a first seed layer and a second seed layer in order to help manufacture the vias. The first seed layer is then patterned into a ring structure which also exposes at least a portion of the first seed layer.

Abstract: Circuits, methods, and system for DC voltage conversion are disclosed. A charge pump circuit is described that includes input switches and output switches that are individually controlled by different clock signals to alternatively couple energy storage capacitors to an input and to an output. The individualized switching control allows for the use of clock signals with no overlapping transitions to improve conversion efficiency. Additionally, the input switches are controlled by clock signals that are level shifted relative to the input voltage. The level shifted switching control also improves efficiency and allows for a range in input voltages to be accommodated for DC voltage conversion.

Abstract: Semiconductor devices and fabrication methods thereof are provided. An exemplary fabrication method includes providing a semiconductor substrate; forming a plurality of fins on a surface of the semiconductor substrate; forming an isolation flowable layer covering the plurality of fins over the semiconductor substrate; performing a first annealing process to turn the isolation flowable layer into an isolation film; and forming first well regions and second well regions in the fins and the semiconductor substrate. The second well regions are at two sides of the first well regions and contact with the first well regions; the first well regions have a first type of well ions; the second well regions have a second type of well ions; and the first type is opposite to the second type in the conductivities.

Abstract: A transceiver control circuit of a transceiver is disclosed including: a receiver circuit; a transmitter circuit; a shared filtering circuit shared by the receiver circuit and the transmitter circuit; a first mode-switch for switching signal input paths of the shared filtering circuit; a second mode-switch for switching signal output paths of the shared filtering circuit; a mode-switch control circuit for controlling the first mode-switch and the second mode-switch; a short-circuit switch coupled between two output terminals of a filter within the shared filtering circuit; and a short-circuit switch control circuit. In a period during which the transceiver transits from a receiving mode to a transmitting mode, the short-circuit switch control circuit turns on the short-circuit switch for a certain period and then turns off the short-circuit switch.

Abstract: A skew compensation circuit includes a common mode generator, a common mode comparator, a common mode detector, and a skew adjustment circuit. The common mode generator generates a common mode voltage according to a first input voltage and a second input voltage. The common mode comparator generates a first comparison voltage and a second comparison voltage according to the common mode voltage. The common mode detector generates a first control voltage, a second control voltage, a third control voltage, and a fourth control voltage according to the first comparison voltage, the second comparison voltage, a first data voltage, and a second data voltage. The skew adjustment circuit generates a first output voltage and a second output voltage according to the first data voltage, the second data voltage, the first control voltage, the second control voltage, the third control voltage, and the fourth control voltage.

Abstract: An object is to manufacture a semiconductor device including an oxide semiconductor film, which has stable electric characteristics and high reliability. A crystalline oxide semiconductor film is formed, without performing a plurality of steps, as follows: by utilizing a difference in atomic weight of plural kinds of atoms included in an oxide semiconductor target, zinc with low atomic weight is preferentially deposited on an oxide insulating film to form a seed crystal including zinc; and tin, indium, or the like with high atomic weight is deposited on the seed crystal while causing crystal growth. Further, a crystalline oxide semiconductor film is formed by causing crystal growth using a seed crystal with a hexagonal crystal structure including zinc as a nucleus, whereby a single crystal oxide semiconductor film or a substantially single crystal oxide semiconductor film is formed.

Abstract: The present invention provides a peeling off method without giving damage to the peeled off layer, and aims at being capable of peeling off not only a peeled off layer having a small area but also a peeled off layer having a large area over the entire surface at excellent yield ratio. The metal layer or nitride layer 11 is provided on the substrate, and further, the oxide layer 12 being contact with the foregoing metal layer or nitride layer 11 is provided, and furthermore, if the lamination film formation or the heat processing of 500° C. or more in temperature is carried out, it can be easily and clearly separated in the layer or on the interface with the oxide layer 12 by the physical means.

Abstract: A display device with less light leakage and excellent contrast is provided. A display device having a high aperture ratio and including a large-capacitance capacitor is provided. A display device in which wiring delay due to parasitic capacitance is reduced is provided. A display device includes a transistor over a substrate, a pixel electrode connected to the transistor, a signal line electrically connected to the transistor, a scan line electrically connected to the transistor and intersecting with the signal line, and a common electrode overlapping with the pixel electrode and the signal line with an insulating film provided therebetween. The common electrode includes stripe regions extending in a direction intersecting with the signal line.

Abstract: Provided are a low-cost semiconductor device manufacturing method and a semiconductor device made using the method. The method includes forming multiple body regions in a semiconductor substrate, forming multiple gate insulating layers and multiple gate electrodes in the body region; implementing a blanket ion implantation in an entire surface of the substrate to form a low concentration doping region (LDD region) in the body region without a mask, forming a spacer at a side wall of the gate electrode, and implementing a high concentration ion implantation to form a high concentration source region and a high concentration drain region around the LDD region. According to the examples, devices have favorable electrical characteristics and at the same time, manufacturing costs are reduced. Since, when forming high concentration source region and drain regions, tilt and rotation co-implants are applied, an LDD masking step is potentially omitted.

Abstract: A dynamic over voltage protection OVP system for limiting an output voltage at an output of a voltage regulation system is described. The dynamic OVP system contains an enabling device and an output voltage limiting device which are communicatively coupled to each other. The enabling device detects a load release at the output of the external voltage regulation system and generates an enable signal based on the detection. The output voltage limiting device receives the enable signal and limits the output voltage based on the enable signal. In this way, the voltage fluctuation at the output of the voltage regulation system is reduced when a subsequent load step occurs e.g. when a load is re-connected to the output of the voltage regulation system.

Abstract: A trench-gate MOSFET is disclosed. A plurality of trenches penetrating through a well region are formed in a semiconductor substrate, and horizontal widths of the trenches are defined by first openings formed. The trenches are filled with polysilicon gates. The first openings at the tops of the polysilicon gates are filled with a first dielectric layer. Under the self-alignment definition of the first dielectric layer, the portions, between the first openings, of the hard mask layer are removed to form second openings. First inner spacers are formed through self-alignment on inner sides of the second openings, and the second openings are narrowed by the first inner spacers to form third openings. The third openings are filled with a metal layer, so that a source contact hole is formed through self-alignment at the top of the source region. A method for manufacturing a trench-gate MOSFET is further disclosed.

Abstract: A structure and a formation method of a semiconductor device are provided. The method includes forming an adhesive layer over a semiconductor substrate and forming a magnetic element over the adhesive layer. The method also includes forming an isolation element extending across the magnetic element. The isolation element partially covers the top surface of the magnetic element and partially covers sidewall surfaces of the magnetic element. The method further includes partially removing the adhesive layer such that an edge of the adhesive layer is laterally disposed between an edge of the magnetic element and an edge of the isolation element. In addition, the method includes forming a conductive line over the isolation element.

Abstract: A highly reliable semiconductor device is provided. The semiconductor device includes a first oxide; a second oxide, a first layer, and a second layer over the first oxide; an insulator over the second oxide; a first conductor over the insulator; a second conductor over the first layer; and a third conductor over the second layer. Each of the first and second layers includes a region with a thickness ranging from 0.5 nm to 3 nm. Each of the second and third conductors contains a conductive material having the physical property of extracting hydrogen.

Abstract: A radio-frequency (RF) switching system for 5G communications and a method of designing it are disclosed. The RF switching system includes a MMMB switching unit and an antenna. The MMMB switching unit includes a 5G-mode multiband switching subunit including a 5G-mode low-frequency (LF)-band switching subunit and a 5G-mode high-frequency (HF)-band switching subunit partitioned from the 5G-mode LF-band switching subunit at a reference frequency. The 5G-mode LF-band switching subunit is connected to the antenna via a low-pass filter, and the 5G-mode HF-band switching subunit is connected to the antenna via a high-pass filter. The RF switching system for 5G communications has improved isolation performance in both the HF and LF bands and improved insertion loss performance in the HF band.

Abstract: A semiconductor device package includes a substrate, a first insulation layer and an electrical contact. The first insulation layer is disposed on the first surface of the substrate. The electrical contact is disposed on the substrate and has a first portion surrounded by the first insulation layer and a second portion exposed from the first insulation layer, and a neck portion between the first portion and the second portion of the electrical contact. Further, the second portion tapers from the neck portion.

Abstract: Power consumption of a display device is reduced. Display quality of a display device is improved. A high-quality image can be displayed regardless of a usage environment. The display device includes a first display element, a second display element, and a control portion. The first display device reflects visible light. The second display element emits visible light. The control portion is configured to drive the first display element and the second display element at the same time such that a maximum value of luminance of light emitted from the second display element is greater than or equal to 1% and less than or equal to 50% of maximum luminance on the assumption that maximum luminance of light which is emitted from the second display element is 100%.

Abstract: A radiation source apparatus is provided. The radiation source apparatus includes a chamber, a target droplet generator, an exhaust module, a measuring device, and a controller. The target droplet generator is configured to provide a plurality of target droplets to the chamber. The exhaust module is configured to extract debris corresponding to the target droplets out of the chamber according to a first gas flow rate. The measuring device is configured to measure concentration of the debris in the chamber. The controller is configured to adjust the first gas flow rate according to the measured concentration of the debris.

Abstract: A device includes an interposer, a plurality of conductive through vias (TVs), a conductive element, and a redistribution line (RDL). The conductive TVs extend from a bottom surface of the interposer to a top surface of the interposer. The conductive element is over the bottom surface of the interposer. The RDL is over the top surface of the interposer. The RDL, the conductive TVs, and the conductive element are connected to form an inductor.

Abstract: A semiconductor package and a manufacturing method thereof are provided. The semiconductor package includes a first chip, a second chip, self-aligned structures, a bridge structure, and an insulating encapsulant. The first chip has a first rear surface opposite to a first active surface. The second chip is disposed beside the first chip and has a second rear surface opposite to a second active surface. The self-aligned structures are disposed on the first rear surface of the first chip and the second rear surface of the second chip. The bridge structure is electrically connected to the first chip and the second chip. The insulating encapsulant covers at least the side surfaces of the first and second chips, a side surface of the semiconductor substrate, and the side surfaces of the self-aligned structures.