Abstract: A device may include a P-N diode, formed within a SiC substrate. The device may include an N-type region formed within the SiC substrate, a P-type region, formed in an upper portion of the N-type region; and an implanted N-type layer, the implanted N-type layer being disposed between the P-type region and the N-type region.

Abstract: This application relates to the transfer of audio data, and in particular to the verification that data transmitted to a data processing module, such as voice biometric module (111), did originate from a microphone. A microphone authentication apparatus (204) is described having a first input for receiving analogue audio signals from a microphone transducer (201) and an analogue-to-digital converter (202) coupled to said first input for generating digital microphone data based on the received audio signals. A data authentication module (203) generates an authentication certificate (MAC) for certifying that the digital microphone data did pass via the authentication module. The authentication certificate is based on the digital microphone data (DM) and an authentication module key. An output module outputs a digital microphone audio signal based on the digital microphone data with the authentication certificate.

Abstract: Structures and formation methods of a chip package are provided. The method includes forming multiple conductive structures over a carrier substrate. The method also includes disposing a semiconductor die over the carrier substrate such that the conductive structures surround the semiconductor die. The method further includes forming a protective layer to surround the conductive structures and the semiconductor die. In addition, the method includes disposing a shielding element over the semiconductor die and the conductive structures. The shielding element is electrically connected to the conductive structures.

Abstract: A method for storage a workpiece used in fabrication of a semiconductor device includes disposing the workpiece on a workpiece carrier, disposing the workpiece carrier with the workpiece in a workpiece container via a workpiece storage system, identifying a content of the workpiece container, and adjusting a storage condition inside the workpiece container in response to the content of the workpiece container via the workpiece storage system.

Abstract: A method of speaker recognition comprises: receiving an audio signal comprising speech; performing a biometric process on a first part of the audio signal, wherein the first part of the audio signal extends over a first time period; obtaining a speaker recognition score from the biometric process for the first part of the audio signal; performing a biometric process on a plurality of second parts of the audio signal, wherein the second parts of the audio signal are successive sections of the first part of the audio signal, and wherein each second part of the audio signal extends over a second time period and the second time period is shorter than the first time period; obtaining a respective speaker recognition score from the biometric process for each second part of the audio signal; and determining whether there has been a speaker change based on the respective speaker recognition scores for successive second parts of the audio signal.

Abstract: A flexible display is provided. The flexible display includes a flexible panel and a backboard body fixedly connected with the flexible panel. A glue-free surface is disposed on a side of the backboard body away from the flexible panel, and the backboard body includes a first backboard and a second backboard. At least one mark is disposed on the glue-free surface of the first backboard and the glue-free surface of second backboard, and all of the marks on the same backboard are arranged along a length direction of a bending line.

Abstract: Systems, methods, and devices implement direct current (DC)-DC converters having fast wake up times and low ripple effects. Methods include determining a DC-DC converter is to be transitioned from an operational mode to a low power mode, and storing a voltage at an input of a comparator coupled to an input of a charge pump, the voltage being stored in a feedback capacitor of a feedback regulation loop. The methods further include uncoupling a voltage trimming circuit from the input of the comparator, and maintaining, at least in part, the stored voltage at the feedback capacitor during the low power mode.

Abstract: A package structure and method for forming the same are provided. The package structure includes a first redistribution structure formed over a substrate, and the first redistribution structure includes a first conductive line, a second conductive line and a first overlapping conductive line between the first conductive line and the second conductive line. The first conductive line has a first width, the second conductive line which is parallel to the first conductive line has a second width, and the overlapping conductive line has a third width which is greater than the first width and the second width. The package structure includes a first package unit formed over the first redistribution structure, and the first package unit includes a first semiconductor die and a first die stack, and the first semiconductor die has a different function than the first die stack.

Abstract: A floating body SRAM cell that is readily scalable for selection by a memory compiler for making memory arrays is provided. A method of selecting a floating body SRAM cell by a memory compiler for use in array design is provided.

Abstract: A substrate panel structure includes a plurality of sub-panels and a dielectric portion. Each of the sub-panels includes a plurality of substrate units. The dielectric portion is disposed between the sub-panels.

Abstract: A method for forming a chip package structure is provided. The method includes forming a conductive structure over a substrate. The substrate includes a dielectric layer and a wiring layer in the dielectric layer, and the conductive structure is electrically connected to the wiring layer. The method includes forming a first molding layer over the substrate and surrounding the conductive structure. The method includes forming a redistribution structure over the first molding layer and the conductive structure. The method includes bonding a chip structure to the redistribution structure.

Abstract: A method for authenticating a user of an electronic device is disclosed. The method comprises: responsive to detection of a trigger event indicative of a user interaction with the electronic device, generating an audio probe signal to play through an audio transducer of the electronic device; receiving a first audio signal comprising a response of the user's ear to the audio probe signal; receiving a second audio signal comprising speech of the user; and applying an ear biometric algorithm to the first audio signal and a voice biometric algorithm to the second audio signal to authenticate the user as an authorised user.

Abstract: A wafer boat includes at least one support member, at least one set of at least one first fixture member, at least one set of at least one second fixture member, and at least one set of at least one third fixture member. The support member extends in a direction. The set of the first fixture member, the set of the second fixture member, and the set of the third fixture member are supported by the support member and sequentially arranged in the direction. The set of the first fixture member is separated from the set of the second fixture member by a first pitch, and the set of the second fixture member is separated from the set of the third fixture member by a second pitch, in which the first pitch is smaller than the second pitch.

Abstract: The present disclosure provides a bio-field effect transistor (BioFET) device and methods of fabricating a BioFET and a BioFET device. The method includes forming a BioFET using one or more process steps compatible with or typical to a complementary metal-oxide-semiconductor (CMOS) process. The BioFET device includes a gate structure disposed on a first surface of a substrate and an interface layer formed on a second surface of the substrate. The substrate is thinned from the second surface to expose a channel region before forming the interface layer.

Abstract: A semiconductor device includes a substrate, a first gate structure, a plurality of first gate spacers, a second gate structure, and a plurality of second gate spacers. The substrate has a first fin structure and a second fin structure. The first gate structure is over the first fin structure, in which the first gate structure includes a first high dielectric constant material and a first metal. A bottom surface of the first high dielectric constant material is higher than bottom surfaces of the first gate spacers. The second gate structure is narrower than the first gate structure and over the second fin structure, in which the second gate structure includes a second high dielectric constant material and a second metal. A bottom surface of the second high dielectric constant material is lower than bottom surfaces of the second gate spacers.

Abstract: A system and method for accessing redundancy array of independent disks (RAID) are provided. The system is coupled between a central processing unit (CPU), a main memory and the RAID, and includes an arithmetic circuit, a register and a disk controller. The arithmetic circuit is coupled to the CPU and the main memory, and is configured to access data from the main memory. The arithmetic circuit calculates a plurality of syndromes of the data to be written and store the calculated syndromes of the plurality of syndromes into the main memory. The register is coupled to the arithmetic circuit, and is configured to store a calculation progress of the plurality of syndromes need to be calculated by the arithmetic circuit. The disk controller is coupled to the register and the RAID, and is configured to read the calculation progress from the register, and according to the calculation progress, to store the calculated syndromes of the plurality of syndromes from the main memory to the RAID.

Abstract: A method includes forming a source region in a semiconductor substrate, in which the source region has a first type dopant. A channel region is formed in the semiconductor substrate and next to the source region. A drain region is formed in the semiconductor substrate, in which the drain region has a second type dopant different from the first type dopant. A heavily doped region is formed between the source region and the channel region, in which the heavily doped region has the first type dopant, and a dopant concentration of the first type dopant in the heavily doped region is higher than a dopant concentration of the first type dopant in the source region. A gate structure is formed over the channel region. A first low-k spacer is formed extending downwardly along a first sidewall of the gate structure to a top surface of the heavily doped region.

Abstract: A method for forming a bond pad structure includes forming an interconnect structure on a semiconductor device, forming a passivation layer on the interconnect structure, forming at least one opening through the passivation layer, forming an oxidation layer at least in the opening, and forming a pad metal layer on the oxidation layer. A portion of the interconnect structure is exposed by the at least one opening.

Abstract: A semiconductor device package includes a carrier, an electronic component, a protection layer, a conductive layer and an integrated passive device (IPD). The electronic component is disposed on the carrier. The protection layer covers the carrier and the electronic component. The conductive layer is disposed on the protection layer and penetrates the protection layer to be electrically connected to the electronic component. The IPD is disposed on the conductive layer and electrically connected to the electronic component through the conductive layer.

Abstract: A method for forming a semiconductor device is provided. A plurality of trenches are formed in the substrate. An isolation oxide layer is formed in the trenches and on the substrate. A shield polysilicon is deposited in the trenches and on the isolation oxide layer on the substrate. A first etching process is performed to remove a first portion of the shield polysilicon. A first removal process is performed to remove a first portion of the isolation oxide layer. A second etching process is performed to remove a second portion of the shield polysilicon. A second removal process is performed to remove a second portion of the isolation oxide layer. An inter-poly oxide layer is formed on the remaining shield polysilicon and the remaining isolation oxide layer, wherein the inter-poly oxide layer has a concave top surface.