Abstract: A method for manufacturing a semiconductor structure is disclosed. The method includes: providing a semiconductor substrate having a plurality of dies thereon; dispensing an underfill material and a molding compound to fill spaces beneath and between the dies; disposing a temporary carrier over the dies; thinning a thickness of the semiconductor substrate; performing back side metallization upon the thinned semiconductor substrate; removing the temporary carrier; and attaching a plate over the dies. An associated semiconductor structure is also disclosed.

Abstract: A power transistor device including a substrate structure, a first conductive layer, a second conductive layer, and a third conductive layer is provided. The substrate structure has a base portion and fin portions. The fin portions protrude from a surface of the base portion. The first conductive layer is disposed across the fin portions and has a first side and a second side opposite to each other. The second conductive layer is disposed across the fin portions and is located at the first side of the first conductive layer. The third conductive layer is disposed across the fin portions and is located at the second side of the first conductive layer. The first conductive layer, the second conductive layer, the third conductive layer, and the fin portions are insulated from each other. An extending direction of the first, second, and third conductive layers intersects a length direction of the fin portions.

Abstract: A cup wash disk for cleaning a photoresist process tool is provided. An upper plate is arranged over a lower plate to define a cavity between the upper and lower plates. The lower plate comprises peripheral openings in fluid communication with the cavity and arranged along a periphery of the lower plate. A plurality of shims is arranged between the upper and lower plates to space the upper and lower plates and to define slits between the upper and lower plates. The slits are in fluid communication with the cavity. A method for cleaning the photoresist process tool using the cup wash disk is also provided.

Abstract: Cooling devices, packaged semiconductor devices, and methods of packaging semiconductor devices are disclosed. In some embodiments, a cooling device for a semiconductor device includes a reservoir having a first plate and a second plate coupled to the first plate. A cavity is between the first plate and the second plate. A phase change material (PCM) is in the cavity. The cooling device is adapted to dissipate heat from a packaged semiconductor device.

Abstract: The present disclosure provides a semiconductor structure, including an Nth metal layer over a transistor region, where N is a natural number, and a bottom electrode over the Nth metal layer. The bottom electrode comprises a bottom portion having a first width, disposed in a bottom electrode via (BEVA), the first width being measured at a top surface of the BEVA, and an upper portion having a second width, disposed over the bottom portion. The semiconductor structure also includes a magnetic tunneling junction (MTJ) layer having a third width, disposed over the upper portion, a top electrode over the MTJ layer and an (N+1)th metal layer over the top electrode. The first width is greater than the third width.

Abstract: The present invention provided a flexible OLED display panel including a flexible substrate, a plurality of OLED devices disposed on the flexible substrate, and a thin-film encapsulating layer disposed on a surface of the OLED devices. The thin-film encapsulating layer includes at least two separate thin-film encapsulating units, the at least two thin-film encapsulating units cover the surface of the OLED devices opposite to the flexible substrate in a form of an one-dimensional array or a two-dimensional array, a gap is formed between edges of two of the thin-film encapsulating units adjacent to each other, and an extension direction of the gap is perpendicular to a bending direction of the flexible OLED display panel.

Abstract: Presented herein is a WLCSP intermediate structure and method forming the same, the method comprising forming a first redistribution layer (RDL) on a carrier, the first RDL having mounting pads disposed on the first RDL, and mounting interposer dies on a second side of the first RDL. A second RDL is formed over a second side of the interposer dies, the second RDL having a first side adjacent to the interposer dies, one or more lands disposed on the second RDL, at least one of the one or more lands in electrical contact with at least one of the interposer dies or at least one of the mounting pads. A molding compound is formed around the interposer dies and over a portion of the first RDL prior to the forming the second RDL and the second RDL is formed over at least a portion of the molding compound.

Abstract: An array substrate, a display panel and a method of manufacturing array substrate are provided. The array substrate, comprising first substrate and data line, data line positioned on first substrate; auxiliary electrode positioned on first substrate, auxiliary electrode for electrically connecting to color filter, vertical projection of auxiliary electrode on first substrate does not intersect with data line; insulating layer positioned on surface of auxiliary electrode which away first substrate, insulating layer has hole; and shielding electrode comprises main section and protrusion section are integrated, main section is located on lateral side of data line which away first substrate, and vertical projection of main section on first substrate is covering data line, protrusion section is positioned on insulating layer, and protrusion section pass through hole and contacting to auxiliary electrode. It achieves to highly product yield and saving production costs.

Abstract: A semiconductor structure includes a semiconductive substrate having a top surface, a III-V compound layer covering the top surface, and a passivation layer having a lower portion and an upper portion, both comprising at least one of oxide and nitride over the III-V compound layer. The semiconductor structure also includes an etch stop layer between the lower portion and the upper portion of the passivation layer, and a gate stack penetrating through the etch stop layer and landing on the lower portion of the passivation layer. The gate stack is surrounded by the etch stop layer.

Abstract: An interconnect structure and a method of forming an interconnect structure are disclosed. The interconnect structure includes a low-k (LK) dielectric layer over a substrate; a first conductive feature in the LK dielectric layer, wherein the first conductive feature has a first sidewall, a second sidewall facing the first sidewall, and a first bottom surface contacting the LK dielectric layer; a first dielectric feature along an upper portion of the first sidewall, wherein a length of the first dielectric feature is at least 10 percent less than a length of the first sidewall; and a second dielectric feature along an upper portion of the second sidewall. The interconnect structure may also include a second conductive feature adjacent to the first conductive feature in the LK dielectric layer.

Abstract: An embodiment is a structure comprising a substrate, a high energy bandgap material, and a high carrier mobility material. The substrate comprises a first isolation region and a second isolation region. Each of first and second isolation regions extends below a first surface of the substrate between the first and second isolation regions. The high energy bandgap material is over the first surface of the substrate and is disposed between the first and second isolation regions. The high carrier mobility material is over the high energy bandgap material. The high carrier mobility material extends higher than respective top surfaces of the first and second isolation regions to form a fin.

Abstract: The disclosure relates to a fin field effect transistor (FinFET) formed in and on a substrate having a major surface. The FinFET includes a fin structure protruding from the major surface, which fin includes a lower portion, an upper portion, and a middle portion between the lower portion and upper portion, wherein the fin structure includes a first semiconductor material having a first lattice constant; a pair of notches extending into opposite sides of the middle portion; and a semiconductor liner adjoining the lower portion. The semiconductor liner is a second semiconductor material having a second lattice constant greater than the first lattice constant.

Abstract: An integrated circuit device includes a semiconductor substrate, and a semiconductor strip extending into the semiconductor substrate. A first and a second dielectric region are on opposite sides of, and in contact with, the semiconductor strip. Each of the first dielectric region and the second dielectric region includes a first portion level with the semiconductor strip, and a second portion lower than the semiconductor strip. The second portion further includes a portion overlapped by the semiconductor strip.

Abstract: Memories with symmetric read current profiles are provided. A memory includes a first memory array formed by a plurality of memory cells, a second memory array formed by a plurality of memory cells, and a read circuit. The read circuit includes a first decoder coupled to the first memory array, a second decoder coupled to the second memory array, and an output buffer. The first decoder obtains first data from the first memory array according a first address signal. The second decoder obtains second data from the second memory array according the first address signal. The output buffer selectively provides the first data or the second data as an output according to a control signal. The first data is complementary to the second data.

Abstract: Methods and apparatus for forming a bond pad of a semiconductor device such as a backside illuminated (BSI) image sensor device are disclosed. The substrate of a device may have an opening at the backside, through the substrate reaching the first metal layer at the front side of the device. A buffer layer may be formed above the backside of the substrate and covering sidewalls of the substrate opening. A pad metal layer may be formed above the buffer layer and in contact with the first metal layer at the bottom of the substrate opening. A bond pad may be formed in contact with the pad metal layer. The bond pad is connected to the pad metal layer vertically above the substrate, and further connected to the first metal layer of the device at the opening of the substrate.

Abstract: A light-emitting element with a lower voltage and higher emission efficiency is provided. The light-emitting element includes a first organic compound, a second organic compound, and a guest material. The LUMO level of the first organic compound is lower than the LUMO level of the second organic compound, and a difference between them is larger than 0 eV and smaller than or equal to 0.5 eV. Furthermore, the HOMO level of the first organic compound is lower than the HOMO level of the second organic compound. The guest material has a function of converting triplet excitation energy into light emission. The first organic compound and the second organic compound form an exciplex.

Abstract: A method of manufacturing a semiconductor device is provided. A first substrate is bonded with a second substrate. The second substrate is recessed to form a first sidewall and a first cavity laterally defined by the first sidewall. The second substrate is recessed to form a second sidewall and a second cavity laterally defined by the second sidewall. The second substrate is bonded with a third substrate at a first barometric pressure thereby forming the first cavity and the second cavity. The first sidewall is recessed to form a channel from the first cavity to an outer surface of the first sidewall. The third substrate is recessed and the first cavity is exposed to a second barometric pressure different from the first barometric pressure.

Abstract: A method for manufacturing semiconductor devices is provided. A protection layer is conformally deposited over a passivation layer such that the protection layer has a protrusion pattern that protrudes from a top surface of the protection layer. Further, a post-passivation interconnect structure (PPI) is conformally formed on the protection layer such that the PPI structure includes a landing pad region, a protrusion pattern conformal to the protrusion pattern of the protection layer, and a connection line electrically connected to the conductive pad. A solder bump is then placed on the landing pad region in contact with the protrusion pattern of PPI structure. A semiconductor device with bump stop structure is also provided. The protrusion pattern of the PPI structure serves as a bump stop that constrains a ball shift in the placement of the solder bump over the landing pad.

Abstract: A method for testing inter-layer connections is presented. The method entails: providing a test semiconductor device, wherein the test semiconductor device comprises a two-port resistance network; measuring base input resistances on at least one of the first and the second ports of the test semiconductor device for different numbers of resistance links in a defect-free circumstance; obtaining a correspondence relationship between the number of resistance links and the base input resistances; measuring actual input resistances on at least one of the first and the second ports of the test semiconductor device; and determining a position of the resistance link corresponding to the actual input resistances based on the correspondence relationship, wherein the position of the resistance link determines the location of a defect. This method can promptly locate a defect in inter-layer components and can reduce test time and simplify test procedures.

Abstract: A method for forming an image sensor device is provided. The method includes forming a photodetector in a semiconductor substrate and forming a shielding layer over the semiconductor substrate. The method also includes forming a dielectric layer over the shielding layer and partially removing the dielectric layer to form a recess. The method further includes partially removing the shielding layer through the recess. In addition, the method includes forming a filter in the recess after the shielding layer is partially removed.