Abstract: The present disclosure describes a semiconductor structure and a method for forming the same. The method can include forming a recess structure in a substrate and forming a first semiconductor layer over the recess structure. The process of forming the first semiconductor layer can include doping first and second portions of the first semiconductor layer with a first n-type dopant having first and second doping concentrations, respectively. The second doping concentration can be greater than the first doping concentration. The method can further include forming a second semiconductor layer over the second portion of the first semiconductor layer. The process of forming the second semiconductor layer can include doping the second semiconductor layer with a second n-type dopant.

Abstract: Matching circuitry is disclosed for power generation in a plasma processing apparatus or other application. Matching circuitry is provided in a unitary physical enclosure and is configured to provide impedance matching at multiple different frequencies. For example, in a dual frequency implementation, first and second RF generators can provide electromagnetic energy at first and second respective frequencies in a continuous mode or a pulsed mode to matching circuitry that includes first and second circuit portions. The first circuit portion can include one or more first tuning elements configured to receive RF power at a first frequency and provide impedance matching for a first ICP load (e.g., a primary inductive element). The second circuit portion can include one or more second tuning elements configured to receive RF power at a second different frequency and provide impedance matching for a second ICP load (e.g., a secondary inductive element).

Abstract: The present application discloses a display panel. The display panel is defined with a display region and a dummy region and include a first substrate and a second substrate. The first substrate comprises a first black matrix disposed in the display region and a second black matrix disposed in the dummy region. A thickness of the second black matrix is greater than a thickness of the first black matrix such that the dummy region of the first substrate forms a first thickened layer relative to the display region. The second substrate is disposed opposite to the first substrate. The present application can reduce a film thickness difference between the display region and the dummy region, weaken a seesaw effect, and improve poor display on a periphery of the display panel.

Abstract: A semiconductor device with different configurations of contact structures and a method of fabricating the same are disclosed. The semiconductor device includes first and second gate structures disposed on first and second fin structures, first and second source/drain (S/D) regions disposed on the first and second fin structures, first and second contact structures disposed on the first and second S/D regions, and a dipole layer disposed at an interface between the first nWFM silicide layer and the first S/D region. The first contact structure includes a first nWFM silicide layer disposed on the first S/D region and a first contact plug disposed on the first nWFM silicide layer. The second contact structure includes a pWFM silicide layer disposed on the second S/D region, a second nWFM silicide layer disposed on the pWFM silicide layer, and a second contact plug disposed on the pWFM silicide layer.

Abstract: In a method of manufacturing a connector, a first copper pillar layer and a sacrificial copper pillar layer are formed on a temporary bearing plate coated with copper, an etch stop layer is applied on the sacrificial copper pillar layer and electroplated to form a second copper pillar layer, insulating materials is laminated to form a first dielectric layer, a first circuit layer is formed on the first dielectric layer, a second copper pillar layer and a sacrificial copper pillar layer are extended on the first circuit layer, and a sacrificial copper layer is formed on the first circuit layer, insulating material is laminated on the first circuit layer to form a second dielectric layer, the temporary bearing plate is removed, a second and third circuit layers are simultaneously formed on the first and second dielectric layers, and the sacrificial copper layer and the sacrificial copper pillar layer are etched.

Abstract: A semiconductor device that can be miniaturized or highly integrated is provided. The semiconductor device includes a transistor and a capacitor. The transistor includes a metal oxide and a first conductor that is electrically connected to the metal oxide. The capacitor includes a first insulator which is provided over the metal oxide and which the first conductor penetrates; a second insulator provided over the first insulator and including an opening reaching the first insulator and the first conductor; a second conductor in contact with an inner wall of the opening, the first insulator, and the first conductor; a third insulator provided over the second conductor; and a fourth conductor provided over the third insulator. The first insulator has higher capability of inhibiting the passage of hydrogen than the second insulator.

Abstract: A display panel, a manufacturing method thereof and a display device are provided. A thin film transistor layer disposed on a substrate includes a first metal trace at least disposed in a wire replacement region. An encapsulation layer includes an inorganic encapsulation sub-layer, which is disposed on one side of the thin film transistor layer away from the substrate and stacked with an inorganic spacer layer. A touch metal layer includes a touch trace, which is at least disposed in the wire replacement region and electrically connected to the first metal trace. Both the inorganic encapsulation sub-layer and the inorganic spacer layer are not overlapped with the wire replacement region.

Abstract: An analog to digital convertor circuit includes an input circuit and a switched capacitor circuit. The input circuit is configured to selectively drain a first current from a first node or drain a second current from a second node according to a first bit and a second bit that have opposite logic values. The switched capacitor circuit is configured to compensate a capacitance value of one of the first node and the second node according to the first bit and the second bit.

Abstract: A device includes a first and a second stacks of channel layers each extending from a first height to a second height. A first dielectric feature on a first side of the first stack and between the first and the second stacks extends from a third height to a fourth height. A second dielectric feature on a second side of the first stack opposite to the first side extends from the third height to a fifth height. A gate electrode extends continuously across a top surface of the first and the second stacks and extends to a sixth height. The fifth height is above the sixth height, the sixth height is above the second height, the second height is above the fourth height, the fourth height is above the first height, and the first height is above the third height.

Abstract: The safety is ensured in such a manner that with an abnormality detection system of a secondary battery, abnormality of a secondary battery is detected, for example, a phenomenon that lowers the safety of the secondary battery is detected early, and a user is warned or the use of the secondary battery is stopped. The abnormality detection system of the secondary battery determines whether the temperature of the secondary battery is within a temperature range in which normal operation can be performed on the basis of temperature data obtained with a temperature sensor. In the case where the temperature of the secondary battery is high, a cooling device is driven by a control signal from the abnormality detection system of the secondary battery. The abnormality detection system of the secondary battery includes at least a memory means. The memory means has a function of holding an analog signal and includes a transistor using an oxide semiconductor for a semiconductor layer.

Abstract: A transistor includes a gate structure that has a first gate dielectric layer and a second gate dielectric layer. The first gate dielectric layer is disposed over the substrate. The first gate dielectric layer contains a first type of dielectric material that has a first dielectric constant. The second gate dielectric layer is disposed over the first gate dielectric layer. The second gate dielectric layer contains a second type of dielectric material that has a second dielectric constant. The second dielectric constant is greater than the first dielectric constant. The first dielectric constant and the second dielectric constant are each greater than a dielectric constant of silicon oxide.

Abstract: A light emitting element unit includes three light emitting elements. A first light emitting element 10a is obtained by laminating a 1a-th electrode 21a, a first organic layer 23a including a first light emitting layer, a 2a-th electrode 22a, a second organic layer 23b including a second light emitting layer, and a third organic layer 23c including a third light emitting layer. A second light emitting element 10b is obtained by laminating the first organic layer 23a, a 1b-th electrode 21b, the second organic layer 23b, a 2b-th electrode 22b, and the third organic layer 23c. A third light emitting element 10c is obtained by laminating the first organic layer 23a, the second organic layer 23b, a 1c-th electrode 21c, the third organic layer 23c, and a 2c-th electrode 22c.

Abstract: Provided is a ferroelectric memory device having a multi-layer stack disposed over a substrate and including a plurality of conductive layers and a plurality of dielectric layers stacked alternately. A channel layer penetrates through the plurality of conductive layers and the plurality of dielectric layers. A plurality of ferroelectric portions are discretely disposed between the channel layer and the plurality of conductive layers. The plurality of ferroelectric portions are vertically separated from one another by one or more non-zero distances.

Abstract: A semiconductor device includes a gate stack and a channel layer over the gate stack. The gate stack includes a metal gate electrode, a ferroelectric layer, and a semiconducting oxide layer disposed between the ferroelectric layer and the metal gate electrode. The semiconducting oxide layer includes SrRuO3, InGaZnO (IGZO) or LaSrMnO.

Abstract: Semiconductor structures including active fin structures, dummy fin structures, epitaxy layers, a Ge containing oxide layer and methods of manufacture thereof are described. By implementing the Ge containing oxide layer on the surface of the epitaxy layers formed on the source/drain regions of some of the FinFET devices, a self-aligned epitaxy process is enabled. By implementing dummy fin structures and a self-aligned etch, both the epitaxy layers and metal gate structures from adjacent FinFET devices are isolated in a self-aligned manner.

Abstract: An optoelectronic device comprises a plurality of optoelectronic light sources being arranged on a first layer, in particular an intermediate layer being arranged between a cover layer and a carrier layer. The first layer comprises or consists of an at least partially transparent material and each optoelectronic light source of the plurality of optoelectronic light sources comprises an individual light converter for converting light emitted by the associated light source into converted light. The light converter of each optoelectronic light source is arranged on the first layer and/or the associated optoelectronic light source.

Abstract: A transmission device according to the present disclosure includes: a data generator configured to generate image data including, as image information, pixel value information obtained by imaging pixels and control information; and a transmission unit configured to transmit the image data.

Abstract: A semiconductor device includes an insulating layer embedding a gate electrode and overlying a substrate, a stack of a gate dielectric including a gate dielectric material, a dielectric diffusion barrier liner including a dielectric diffusion barrier material, and an active layer overlying a top surface of the gate electrode, and a source electrode and a drain electrode contacting a respective portion of a top surface of the active layer. The dielectric diffusion barrier material is different from the gate dielectric material and is selected from a dielectric metal oxide material and a dielectric compound of silicon, and suppresses loss of metallic elements during subsequent anneal processes.

Abstract: A USB chip includes positive and negative data pins, first and second transceiver circuits, a switching circuit, and a control circuit. During a high-speed handshake stage, the control circuit controls the switching circuit to be in a second state to disconnect the positive and negative data pins from a first terminal impedance circuit and actuates the second transceiver circuit to transmit a second voltage signal via the positive and negative data pins alternately. During a high-speed transmission stage, the control circuit controls the switching circuit to be in a first state to connect the positive and negative data pins with the first terminal impedance circuit and actuates the first transceiver circuit to transmit a first voltage signal, which has a first voltage level lower than a voltage level of the second voltage signal, via the positive and negative data pins alternately.

Abstract: The present disclosure provides a precursor solution of an indium gallium zinc oxide film and a method of preparing an indium gallium zinc oxide thin film transistor. The precursor solution is provided with an indium salt, a gallium salt, a zinc salt, a stabilizing agent, and a solvent. The stabilizing agent is ethanolamine. Use of ethanolamine helps to promote an oxidation process of the precursor solution, and reduce an oxygen vacancy concentration in the indium gallium zinc oxide film, so as to improve negative bias of a threshold voltage of a channel layer made of the indium gallium zinc oxide film in a thin film transistor.