Abstract: A highly functional semiconductor device is provided. The semiconductor device includes a first transistor and a second transistor. The first transistor includes a first semiconductor layer, a first gate electrode, a first electrode, and a second electrode. The second transistor includes a second semiconductor layer, a second gate electrode, a third electrode, and a fourth electrode. The first gate electrode and the second gate electrode are connected to each other, and the second electrode and the third electrode are connected to each other. A first insulating layer, a second insulating layer, and a second semiconductor layer are stacked over the first semiconductor layer. The first insulating layer is less likely to diffuse hydrogen than the second insulating layer. The second insulating layer contains oxide, the first semiconductor layer contains polycrystalline silicon, and the second semiconductor layer contains a metal oxide.

Abstract: Provided is an imaging element that includes a semiconductor substrate, a first photoelectric converter, a through electrode, a first dielectric film, and a second dielectric film. The semiconductor substrate has one surface and another surface that are opposed to each other. The semiconductor substrate has a through hole penetrating between the one surface and the other surface. The first photoelectric converter is provided above the one surface of the semiconductor substrate. The through electrode is electrically coupled to the first photoelectric converter and penetrates the semiconductor substrate inside the through hole. The first dielectric film is provided on the one surface of the semiconductor substrate and has a first film thickness. The second dielectric film is provided on a side surface of the through hole and has a second film thickness. The second film thickness is less than the first film thickness.

Abstract: A processing device includes: a receiving module for receiving a configuration from a control device, wherein the configuration includes a destination address, a length, a filled value and a function type; a control module for (A) configuring an access state for accessing a slave device according to the function type and (B) comparing a counting value with the length to generate a comparison result according to the function type, determining whether data received from the slave device reaches an end to generate a determination result, or both; a reading module for reading the data according to the access state; a writing module for writing the filled value to the destination address according to information of the access state, the determination result and the comparison result; and a transmitting module for transmitting an interrupt signal to the control device according to result(s) of the determination result and the comparison result.

Abstract: Control circuitry for the load voltage of a safety-relevant load is sensitive to values of the load voltage outside a safe voltage range. The control circuitry includes a seventh node, a reference potential, a dominant main control circuit, and a non-dominant emergency control circuit. The seventh node is part of the dominant main control circuit, and not part of the non-dominant emergency control circuit. The load voltage of the safety relevant load drops between the seventh node and the reference potential. The dominant main control circuit includes the load voltage as a control parameter, whereas the non-dominant emergency control circuit does not. In the event of an uninterrupted dominant main control circuit, the load voltage depends on the load voltage, and in the event of an interrupted dominant main control circuit, does NOT depend on the load voltage but is controlled nevertheless.

Abstract: A method for manufacturing an embedded package structure having an air resonant cavity according to an embodiment includes manufacturing a first substrate including a first insulating layer, a chip embedded in the insulating layer, and a wiring layer on a terminal face of the chip of the first substrate, wherein the wiring layer is provided thereon with an opening revealing the terminal face of the chip; manufacturing a second substrate which comprises a second insulating layer; locally applying a first adhesive layer on the wiring layer such that the opening revealing the terminal face of the chip is not covered; and applying a second adhesive layer on the second substrate; and attaching and curing the first adhesive layer of the first substrate and the second adhesive layer of the second substrate to obtain an embedded package structure having an air resonant cavity on the terminal face of the chip.

Abstract: Semiconductor structures and methods for manufacturing the same are provided. The semiconductor structure includes a substrate and semiconductor material layers stacked along a first direction over the substrate and spaced apart from each other. The semiconductor structure also includes inner spacers stacked along the first direction in spaces between the semiconductor material layers and a gate structure extending along a second direction and wrapping around the semiconductor material layers. In addition, the gate structure abuts a first side of the inner spacers. The semiconductor structure also includes a source/drain structure formed over the isolating feature and abutting the second side of the inner spacers.

Abstract: A method of removing a hard mask layer includes providing a gate. A hard mask layer covers and contacts a top surface of the gate. Two spacer structures respectively contacts two sides of the gate. Two first spacers are respectively disposed on the two spacer structures. Later, a wet etching process is performed to remove the hard mask layer and the first spacers and keep the spacer structures. An etchant is utilized in the wet etching process. A selective etching ratio of the silicon nitride to silicon oxide of the etchant is more than 90. The etchant includes Si(OH)4. A concentration of Si(OH)4. is greater than or equal to 3.95 ppm and smaller than or equal to 10 ppm.

Abstract: A method for synchronizing analog data (Data_ana1, Data_ana2) at the output of a plurality of digital/analog converters (DAC), comprising at least one conversion core (C1, C2), on an active edge of a common reference clock (Clk), the method comprising the following steps: a) supplying an external synchronization signal (SYNC_ext), to at least one converter, and supplying a signal of the common reference clock to the plurality of converters; b) generating, within each converter, an internal synchronization signal (SYNC_int), such that all the internal synchronization signals are aligned on an active edge of the common reference clock; c) for each of the converters, generating a start signal (START1, START2) which represents the start of the sending of digital data and counting a number of clock strokes until the internal synchronization signal is generated, and; d) applying a delay Ri (R1, R2) to each converter core, the delay being equal to the difference between the highest number counted in step c) and the

Abstract: The prevent disclosure provides a method for forming a reflective mask. In some embodiments, the method includes forming a carbon-containing layer over a substrate; forming a reflective multilayer over the carbon-containing layer; forming an absorption pattern over the reflective multilayer. In some embodiments, the method includes growing a light absorbing layer over a substrate; polishing the light absorbing layer; forming a reflective layer over the polished light absorbing layer; forming an absorption pattern over the reflective layer.

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a substrate. The semiconductor device structure includes a gate stack over the substrate. The gate stack includes a gate dielectric layer, a first metal-containing layer, a silicon-containing layer, a second metal-containing layer, and a gate electrode layer sequentially stacked over the substrate, the silicon-containing layer is between the first metal-containing layer and the second metal-containing layer, and the silicon-containing layer includes an oxide material.

Abstract: A package structure and a formation method of a package structure are provided. The package structure includes a circuit substrate and a die package bonded to the circuit substrate through bonding structures. The package structure also includes a reinforcing structure over the circuit substrate. The reinforcing structure partially surrounds a corner of the die package. The package structure further includes an underfill structure surrounding the bonding structure. The underfill structure is in direct contact with the reinforcing structure.

Abstract: A package structure including a first semiconductor die, a second semiconductor die, first conductive pillars and a first insulating encapsulation is provided. The first semiconductor die includes a semiconductor substrate, an interconnect structure and a first redistribution circuit structure. The semiconductor substrate includes a first portion and a second portion disposed on the first portion. The interconnect structure is disposed on the second portion, the first redistribution circuit structure is disposed on the interconnect structure, and the lateral dimension of the first portion is greater than the lateral dimension of the second portion. The second semiconductor die is disposed on the first semiconductor die. The first conductive pillars are disposed on the first redistribution circuit structure of the first semiconductor die. The first insulating encapsulation is disposed on the first portion.

Abstract: Embodiments include nanostructure devices and methods of forming nanostructure devices which include a treatment process to expand a sidewall spacer material to close a seam in the sidewall spacer material after deposition. The treatment process includes oxidation anneal and heat anneal to expand the sidewall spacer material and crosslink the open seam to form a closed seam, lower k-value, and decrease density.

Abstract: An imaging device having a color imaging function and an infrared imaging function is provided. The imaging device has a structure in which a first photoelectric conversion device and a second photoelectric conversion device are stacked, and the second photoelectric conversion device generates electric charge by absorbing infrared light and transmits light having a wavelength of a higher energy than that of infrared light. The first photoelectric conversion device is positioned to overlap with the second photoelectric conversion device, and generates electric charge by absorbing light (visible light) passing through the second photoelectric conversion device. Thus, a subpixel for color imaging and a subpixel for infrared imaging can be positioned to overlap with each other, and an infrared imaging function can be added without a decrease in the definition of color imaging.

Abstract: A light-emitting substrate and a display device are provided. The light-emitting substrate includes a plurality of partitions, and the partitions include a first light-emitting unit and a first dummy unit. The first light-emitting unit includes at least one light-emitting element. The first dummy unit is connected in parallel with the first light-emitting unit. The first dummy unit includes a dummy light-emitting element, and an operating voltage of the first dummy unit is greater than an operating voltage of the first light-emitting unit.

Abstract: According to embodiments of the present disclosure, two-dimensional (2D) materials may be used as nanosheet channels for multi-channel transistors. Nanosheet channels made two-dimensional (2D) materials can achieve the same drive current at smaller dimensions and/or fewer number of channels, therefore enable scaling down and/or boost derive current. Embodiments of the present disclosure also provide a solution of P-type and N-type balancing in a device without increasing footprint of the device.

Abstract: An integrated circuit simulation method is performed by a processor and includes: obtaining a register transfer level (RTL) waveform set obtained by performing an RTL simulation based on a circuit, where the circuit is generated in an RTL design stage and includes a register having an internal net and a data output port, and the RTL waveform set includes a first waveform corresponding to the data output port of the register; obtaining a netlist and delay information obtained by performing a logic synthesis based on the circuit, where the netlist includes a first node and a second node, the first node corresponds to the internal net of the register, and the second node corresponds to the data output port of the register; applying the first waveform to the first node; and triggering the register according to the delay information to obtain a second waveform at the second node.

Abstract: An inductive unit is formed in an integrated circuit. An electromagnetic radiation test is performed thereon. When an amount of electromagnetic radiation exceeds a radiation threshold value, a shielding structure is formed. The shielding structure has a width and a distance separated from the inductive unit such that a decreasing amount of a quality factor of the inductive unit is not larger than a first predetermined value and a shielded amount of electromagnetic radiation is not lower than a second predetermined value. The inductive unit has a symmetric shape and the inductive device further includes a single asymmetric inductive portion. The closed shape of the shielding structure encloses the inductive unit and covers the single asymmetric inductive portion. A part of the single asymmetric inductive portion extends along a peripheral direction of the shielding structure.

Abstract: The present disclosure provides an integrated circuit (IC) structure. The IC structure includes a semiconductor substrate; an interconnection structure formed on the semiconductor substrate; and a redistribution layer (RDL) metallic feature formed on the interconnection structure. The RDL metallic feature further includes a barrier layer disposed on the interconnection structure; a diffusion layer disposed on the barrier layer, wherein the diffusion layer includes metal and oxygen; and a metallic layer disposed on the diffusion layer.

Abstract: An imaging element which is formed by sequentially stacking at least an anode, an anode-side buffer layer, a photoelectric conversion layer, and a cathode, in which the anode-side buffer layer includes a material having structural formula in which thiophene and carbazole are combined.