Abstract: The present document relates to a power converter comprising an inductor, a first stage, and a second stage. The first stage may be coupled between an input of the power converter and the inductor, and the first stage may comprise a first flying capacitor. The second stage may be coupled between the inductor and an output of the power converter, and the second stage may comprise a second flying capacitor. A second terminal of the first flying capacitor may be connected to a first terminal of the inductor, and a first terminal of the second flying capacitor may be connected to a second terminal of the inductor.

Abstract: A substrate support apparatus includes a housing and a plurality of spherical supports. The housing has a top surface, the top surface including a plurality of openings. The housing is configured to position the plurality of spherical supports within the plurality of openings so that topmost surfaces of the plurality of spherical supports are arranged in a plane above the top surface. A spherical support of the plurality of spherical supports is rotatable within the housing.

Abstract: An organic light-emitting diode (OLED) display panel is provided, including an array layer. The array layer includes a first source electrode and a second source electrode that are disposed in contact with each other, and a first drain electrode and a second drain electrode that are disposed in contact with each other. The first source electrode and the first drain electrode are in contact with an active layer through via holes. The first source/drain electrode and the second source/drain electrode are disposed in contact with each other, thereby reducing a probability of abnormal via holes in a source/drain region and facilitating wiring in the source/drain region.

Abstract: In some embodiments, a piezoelectric biosensor is provided. The piezoelectric biosensor includes a semiconductor substrate. A first electrode is disposed over the semiconductor substrate. A piezoelectric structure is disposed on the first electrode. A second electrode is disposed on the piezoelectric structure. A sensing reservoir is disposed over the piezoelectric structure and exposed to an ambient environment, where the sensing reservoir is configured to collect a fluid comprising a number of bio-entities.

Abstract: In an embodiment, a method includes forming a first gate electrode over a substrate. The method also includes forming a first gate dielectric layer over the first gate electrode. The method also includes depositing a semiconductor layer over the first gate dielectric layer. The method also includes forming source/drain regions over the first gate dielectric layer and the semiconductor layer, the source/drain regions overlapping ends of the semiconductor layer. The method also includes forming a second gate dielectric layer over the semiconductor layer and the source/drain regions. The method also includes and forming a second gate electrode over the second gate dielectric layer.

Abstract: An electronic device package and manufacturing method thereof are provided. The electronic device package includes an electronic component including an active surface, a patterned conductive layer disposed on the active surface, an encapsulation layer disposed over the patterned conductive layer, and a buffer layer disposed between the patterned conductive layer and the encapsulation layer. The buffer layer is shaped and sized to alleviate a stress generated due to an interaction between the patterned conductive layer and the encapsulation layer.

Abstract: A perpendicularly magnetized magnetic tunnel junction (p-MTJ) is disclosed wherein a free layer (FL) has a first interface with a MgO tunnel barrier, a second interface with a Mo or W Hk enhancing layer, and is comprised of FexCoyBz wherein x is 66-80, y is 5-9, z is 15-28, and (x+y+z)=100 to simultaneously provide a magnetoresistive ratio >100%, resistance x area product <5 ohm/?m2, switching voltage <0.15V (direct current), and sufficient Hk to ensure thermal stability to 400° C. annealing. The FL may further comprise one or more M elements such as O or N to give (FexCoyBz)wM100-w where w is >90 atomic %. Alternatively, the FL is a trilayer with a FeB layer contacting MgO to induce Hk at the first interface, a middle FeCoB layer for enhanced magnetoresistive ratio, and a Fe or FeB layer adjoining the Hk enhancing layer to increase thermal stability.

Abstract: Disclosed herein are related to a memory array. In one aspect, the memory array includes a set of resistive storage circuits including a first subset of resistive storage circuits connected between a first local line and a second local line in parallel. The first local line and the second local line may extend along a first direction. In one aspect, for each resistive storage circuit of the first subset of resistive storage circuits, current injected at a first common entry point of the first local line exits through a first common exit point of the second local line, such that each resistive storage circuit of the first subset of resistive storage circuits may have same or substantial equal resistive loading.

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a first device formed over a substrate, wherein the first device includes a first fin structure and a first S/D structure formed over the first fin structure. The semiconductor device structure includes a second device formed over or below the first device, and the second device includes a plurality of second nanostructures stacked in a vertical direction. The semiconductor device structure also includes a second S/D structure formed over the second nanostructures, and the second S/D structure is directly above or below the first S/D structure.

Abstract: Disclosed are a touch display panel and a display device, comprising touch wires. The touch wires comprises first sub-parts arranged along the first direction; the first sub-part comprises a first wiring sub-part arranged along the first direction and a first connecting sub-part connecting adjacent first wiring sub-parts. The widths of the two first connecting sub-parts connected to one first wiring sub-part are different, and/or the widths of the two first connecting sub-parts connected between two adjacent first wiring sub-parts are different.

Abstract: A method of supplying a chemical solution to a photolithography system. The chemical solution is pumped from a variable-volume buffer tank. The pumped chemical solution is dispensed in a spin-coater. The variable-volume buffer tank is refilled by emptying a storage container filled with the chemical solution into the variable-volume buffer tank.

Abstract: In one exemplary aspect, a method for semiconductor manufacturing comprises forming first and second silicon nitride features on sidewall surfaces of a contact hole, where the contact hole is disposed in a dielectric layer and above a source/drain (S/D) feature. The method further comprises forming a contact plug in the contact hole, the contact plug being electrically coupled to the S/D feature, removing a top portion of the contact plug to create a recess in the contact hole, forming a hard mask layer in the recess, and removing the first and second silicon nitride features via selective etching to form first and second air gaps, respectively.

Abstract: A device includes a semiconductor die, a source contact, a drain contact, a first passivation layer, a T-shaped gate contact, a field plate, and a second passivation layer. The semiconductor die generally includes a plurality of semiconductor layers disposed on an insulating substrate. The source contact and the drain contact are electrically coupled to a channel formed in the semiconductor layers and defining an active area of the device. The first passivation layer generally covers the active area of the device, the source contact, and the drain contact. The T-shaped gate contact may be disposed within the active area of the device. The T-shaped gate contact is generally electrically separated from the channel and comprises a column portion and a cap portion. The field plate may be disposed above the active area of the device. The field plate is generally adjacent to and laterally separated from the cap portion of the T-shaped gate contact.

Abstract: A lithography method is described. The method includes forming a resist layer over a substrate, performing a treatment on the resist layer to form an upper portion of the resist layer having a first molecular weight and a lower portion of the resist layer having a second molecular weight less than the first molecular weight, performing an exposure process on the resist layer, and performing a developing process on the resist layer to form a patterned resist layer.

Abstract: An object is to provide a semiconductor device which can suppress characteristic deterioration in each transistor without destabilizing operation. In a non-selection period, a transistor is turned on at regular intervals, so that a power supply potential is supplied to an output terminal of a shift register circuit. A power supply potential is supplied to the output terminal of the shift register circuit through the transistor. Since the transistor is not always on in a non-selection period, a shift of the threshold voltage of the transistor is suppressed. In addition, a power supply potential is supplied to the output terminal of the shift register circuit through the transistor at regular intervals. Therefore, the shift register circuit can suppress noise which is generated in the output terminal.

Abstract: The present disclosure provides a packaging method and packaging structure of an FBAR. A second cavity in a resonator cover provided includes a groove in a second substrate and a space surrounded by an elastic bonding material layer. The elastic bonding material layer bonds the resonator cover to a resonant cavity main structure, and elasticity of the elastic bonding material layer is removed after the bonding. Through holes and a conductive interconnection layer on inner surfaces of the through holes are formed on the resonator cover. Since the second cavity includes the groove in the second substrate and the space surrounded by the elastic bonding material layer, which can avoid problems that performance of the elastic bonding material layer is unstable with temperature and humidity changes when the second cavity is entirely surrounded by the elastic bonding material layer, that is, the stability of the resonator is improved.

Abstract: A semiconductor integrated circuit (IC) including a first fin structure having a first aqueous soluble channel layer. The semiconductor IC includes a first gate structure over the first aqueous soluble channel layer, wherein the first gate structure includes a first oxide film directly contacting the first aqueous soluble channel layer, and the first oxide film includes a first material. The semiconductor IC includes a first spacer along the first gate structure, wherein a bottom surface of the first spacer is above an interface between the first oxide layer and the first aqueous soluble channel layer. The semiconductor IC includes a second fin structure having a second aqueous soluble channel layer. The semiconductor IC includes a second gate structure over the second aqueous channel layer, wherein the second gate structure includes a second oxide film directly contacting the second aqueous soluble channel layer, the second oxide film includes a second material.

Abstract: A light-emitting element which uses a plurality of kinds of light-emitting dopants emitting light in a balanced manner and has high emission efficiency is provided. Further, a light-emitting device, a display device, an electronic device, and a lighting device each having reduced power consumption by using the above light-emitting element are provided. A light-emitting element which includes a plurality of light-emitting layers including different phosphorescent materials is provided. In the light-emitting element, the light-emitting layer which includes a light-emitting material emitting light with a long wavelength includes two kinds of carrier-transport compounds having properties of transporting carriers with different polarities. Further, in the light-emitting element, the triplet excitation energy of a host material included in the light-emitting layer emitting light with a short wavelength is higher than the triplet excitation energy of at least one of the carrier-transport compounds.

Abstract: A method of forming a memory circuit includes generating a layout design of the memory circuit, and manufacturing the memory circuit based on the layout design. The generating of the layout design includes generating a first active region layout pattern corresponding to fabricating a first active region of a first pull down transistor, generating a second active region layout pattern corresponding to fabricating a second active region of a first pass gate transistor, and generating a first metal contact layout pattern corresponding to fabricating a first metal contact. The first metal contact layout pattern overlaps the cell boundary of the memory circuit and the first active region layout pattern. The first metal contact electrically coupled to a source of the first pull down transistor. The memory circuit being a four transistor (4T) memory cell including a first and second pass gate transistor, and a first and second pull down transistor.

Abstract: A semiconductor device includes a substrate, a first well region, a second well region, an isolation region, a first resistor segment and a second resistor segment. The substrate includes a region having a first conductivity type. The first and the second well regions are disposed in the region of the substrate. The isolation region is disposed on the first and the second well regions. The first and the second resistor segments are electrically connected to each other and disposed on the isolation region. Moreover, the first and the second well regions are disposed directly under the first and the second resistor segments, respectively. The first and the second well regions do not overlap with each other in a vertical projection direction and have a second conductivity type that is opposite to the first conductivity type.