Abstract: A motor is coupled to a motor control device including a set of high-side switches, a set of low-side switches, a capacitor and a controller. The set of high-side switches and the set of low-side switches are coupled to the motor. The capacitor is coupled to the set of high-side switches. The controller is coupled to the capacitor, the set of high-side switches and the set of low-side switches. A method of braking the motor includes upon the motor being disconnected from an external power source, the controller receiving a supply voltage from the capacitor, turning on the set of low-side switches, turning off the set of high-side switches, and the controller switching the set of low-side switches according to the supply voltage.

Abstract: A semiconductor device includes a semiconductor fin, a gate structure, and a dielectric isolation plug. The semiconductor fin extends along a first direction above a substrate and includes a silicon germanium layer and a silicon layer over the silicon germanium layer. The gate structure extends across the semiconductor fin along a second direction perpendicular to the first direction. The dielectric isolation plug extends downwardly from a top surface of the silicon layer into the silicon germanium layer when viewed in a cross section taken along the first direction.

Abstract: A display device is provided. The display device includes: a flexible screen body including a planar area and a bending area connected to the planar area; a color filter disposed on the flexible screen body and at least covering the planar area; a protective layer disposed on the flexible screen body and at least covering a part of the bending area; and a coverplate disposed on the color filter and at least covering the planar area. The protective layer and the coverplate are arranged at intervals.

Abstract: A provisioning device includes a user interface, a radio transceiver to communicate with a pairable device, and a controller. The controller is configured to initiate a pairing protocol, via the radio transceiver, with the pairable device. The controller is configured to instruct a user, via the user interface, to perform a gesture with the provisioning device or the pairable device. The controller is configured to pair the provisioning device with the pairable device, via the radio transceiver, in response to the performed gesture matching an expected gesture within a threshold level of similarity.

Abstract: A capacitive isolator is developed. Embodiments of the capacitive isolator include a substrate; a shallow trench isolation region coupled to the substrate; a polysilicon layer disposed above the shallow trench isolation region; a bottom metal plate disposed above the polysilicon layer; one or more lower dielectric layers above the bottom metal plate; an intermediate metal plate disposed above the one or more lower dielectric layers; and a top metal plate disposed above the intermediate metal plate. A semiconductor device including two capacitive isolators and an isolation structure disposed between the two capacitive isolators is also developed.

Abstract: The present disclosure provides an electronic device and a method of manufacturing the same. The electronic device includes a first redistribution structure and a first encapsulant. The first encapsulant supports the first redistribution structure and is configured to function as a first reinforcement to provide a second redistribution structure. The redistribution structure has a plurality of conductive layers disposed over the first redistribution structure.

Abstract: A device includes a semiconductor fin, a gate structure, gate spacers, and a dielectric feature. The semiconductor fin is over a substrate. The gate structure is over the semiconductor fin and includes a gate dielectric layer over the semiconductor fin and a gate metal covering the gate dielectric layer. The gate spacers are on opposite sides of the gate structure. The dielectric feature is over the substrate. The dielectric feature is in contact with the gate metal, the gate dielectric layer, and the gate spacers, and an interface between the gate metal and the dielectric feature is substantially aligned with an interface between the dielectric feature and one of the gate spacers.

Abstract: A semiconductor device includes a plurality of semiconductor layers vertically separated from one another. Each of the plurality of semiconductor layers extends along a first lateral direction. The semiconductor device includes a gate structure that extends along a second lateral direction and comprises at least a lower portion that wraps around each of the plurality of semiconductor layers. The lower portion of the gate structure comprises a plurality of first gate sections that are laterally aligned with the plurality of semiconductor layers, respectively, and wherein each of the plurality of first gate sections has ends that each extend along the second lateral direction and present a first curvature-based profile.

Abstract: A cover plate, a manufacturing method of the cover plate, and a display panel are provided. The cover plate covers the display panel and includes a cover plate body and an anti-reflection layer. The anti-reflection layer is provided with anti-reflection particles therein, and an orthographic projection of the anti-reflection particles in the display panel is completely located in a region of each sub-pixel unit. By accurately controlling the distribution position of the particles during the manufacturing process, each particle can completely fall in the corresponding region of each sub-pixel unit, and will not be distributed at a junction position between two adjacent sub-pixel units.

Abstract: An embodiment of the present disclosure provides a flexible display device. The flexible display device includes a display module and a light enhancement layer. The light enhancement layer includes a hardened layer and an anti-reflective layer. A refractive index of the hardened layer is greater than a refractive index of the anti-reflective layer. The light enhancement layer is disposed in a bendable region of the display module to reduce a visual effect of creases, and a film layer structure is changed to reduce the creases of the bendable region and improve a display effect.

Abstract: A device incudes a substrate. A first fin and a second fin are over the substrate. An isolation structure is laterally between the first fin and the second fin. A gate structure crosses the first fin and the second fin. A first source/drain epitaxy structure is over the first fin. A second source/drain epitaxy structure is over the second fin. A spacer layer extends from a first sidewall of the first fin to a first sidewall of the second fin along a top surface of the isolation structure.

Abstract: A semiconductor device includes a pixel electrode and a transistor which includes a first gate electrode, a first insulating layer over the first gate electrode, a semiconductor layer over the first insulating layer, a second insulating layer over the semiconductor layer, and a second gate electrode. The pixel electrode and the second gate electrode are provided over the second insulating layer. The first gate electrode has a region overlapping with the semiconductor layer with the first insulating layer provided therebetween. The second gate electrode has a region overlapping with the semiconductor layer with the second insulating layer provided therebetween. A first region is at least part of a region where the second gate electrode overlaps with the semiconductor layer. A second region is at least part of a region where the pixel electrode is provided. The second insulating layer is thinner in the first region than in the second region.

Abstract: The present disclosure provides a semiconductor substrate, including a first dielectric layer with a first surface and a second surface, a first conductive via extending between the first surface and the second surface, a first patterned conductive layer on the first surface, and a second patterned conductive layer on the second surface. The first conductive via includes a bottom pattern on the first surface and a second patterned conductive layer on the second surface. The bottom pattern has at least two geometric centers corresponding to at least two geometric patterns, respectively, and a distance between one geometric center and an intersection of the two geometrical patterns is a geometric radius. A distance between the at least two geometric centers is greater than 1.4 times the geometric radius. A method for manufacturing the semiconductor substrate described herein and a semiconductor package structure having the semiconductor substrate are also provided.

Abstract: An apparatus and a method for performing debug control in a chip are provided, wherein the apparatus includes a first counter, a first determination circuit, a second counter and a second determination circuit. The first counter counts a number of execution times of a specific system request in the chip to generate a first counting result, and the first determination circuit generates a first determination result according to the first counting result. The second counter counts a number of cycles of an execution clock to generate a second counting result, and the second determination circuit generates a second determination result according to the second counting result. When the first determination result indicates that the first counting result reaches a first threshold and the second determination result indicates that the second counting result reaches a second threshold, execution of the chip is suspended at a breakpoint state.

Abstract: A display panel and a corresponding driving method are provided, including at least an N?1th stage demultiplexing subcircuit and an Nth stage demultiplexing subcircuit. The N?1th stage demultiplexing subcircuit includes at least M N?1th stage demultiplexing units, wherein M and N are both integers not less than 2. By disposing at least two stages of the demuxing subcircuits in cascade, one signal can time-sharingly multiplex to a plurality of signals and correspondingly exponentially reduce a number of signal wirings.

Abstract: A package structure including a first semiconductor die, at least one second semiconductor die conductive terminals and an insulating encapsulation is provided. The at least one second semiconductor die is stacked on and electrically connected to the first semiconductor die. The conductive terminals are disposed on and electrically connected to the first semiconductor die. The insulating encapsulation laterally encapsulates the first semiconductor die, the at least one second semiconductor die and the conductive terminals, wherein the conductive terminals protrude from a surface of the insulating encapsulation. Furthermore, a method for forming the above-mentioned is also provided.

Abstract: A pixel driving circuit, a driving method of the pixel driving circuit, and a display panel are disclosed. The pixel driving circuit includes a first transistor having a first electrode electrically connected to a first voltage terminal, having a second electrode electrically connected to an anode of a light-emitting device and electrically connected to a second voltage terminal via the light-emitting device; a second transistor having a source and a drain electrically connected between a data line and the second electrode of the first transistor; and a third transistor having a source and a drain electrically connected between a gate of the first transistor and the first electrode of the first transistor.

Abstract: A semiconductor device including a substrate, a low-k dielectric layer, a cap layer, and a conductive layer is provided. The low-k dielectric layer is disposed over the substrate. The cap layer is disposed on the low-k dielectric layer, wherein a carbon atom content of the cap layer is greater than a carbon atom content of the low-k dielectric layer. The conductive layer is disposed in the cap layer and the low-k dielectric layer.

Abstract: A device includes a dielectric layer, a plurality of grating structures, and a dielectric material between the plurality of grating structures and on top of the plurality of grating structures. The grating structures are arranged on the dielectric layer and separated from each other, the plurality of grating structures each having a bottom portion and top portion, the top portion having a first width and the bottom portion having a second width, the second width being larger than the first width.

Abstract: A semiconductor structure and a manufacturing method thereof are provided. The method includes: providing a patterned substrate, where the patterned substrate includes columnar structures; providing second inhibition layers, where the second inhibition layers are respectively located between two adjacent columnar structures of the columnar structures, and upper surfaces of the columnar structures are exposed; providing a light-emitting structure layer on the upper surface of each of the columnar structures; and removing the patterned substrate, to obtain holes at regions corresponding to the columnar structures, where the holes are respectively located between two adjacent second inhibition layers of the second inhibition layers, and the holes correspond to the light-emitting structure layers respectively. The manufacturing method provided by the present disclosure optimizes the manufacturing process and realizes full-color LED.