Abstract: When a PCI-bus controller receives a request from a PCI-bus master to transfer data with an address in secondary memory, the controller performs an initial inquire cycle and withholds TRDY# to the PCI-bus master until any write-back cycle completes. The controller then allows the burst access to take place between secondary memory and the PCI-bus master, and simultaneously and predictively, performs an inquire cycle of the L1 cache for the next cache line. In this manner, if the PCI burst continues past the cache line boundary, the new inquire cycle will already have taken place, or will already be in progress, thereby allowing the burst to proceed with, at most, a short delay. Predictive snoop cycles are not performed if the first transfer of a PCI-bus master access would be the last transfer before a cache line boundary is reached.

Abstract: When a PCI-bus controller receives a request from a PCI-bus master to transfer data with an address in secondary memory, the controller performs an initial inquire cycle and withholds TRDY# to the PCI-bus master until any write-back cycle completes. The controller then allows the burst access to take place between secondary memory and the PCI-bus master, and simultaneously and predictively, performs an inquire cycle of the L1 cache for the next cache line. In this manner, if the PCI burst continues past the cache line boundary, the new inquire cycle will already have taken place, or will already be in progress, thereby allowing the burst to proceed with, at most, a short delay. Predictive snoop cycles are not performed if the first transfer of a PCI-bus master access would be the last transfer before a cache line boundary is reached.

Abstract: When a PCI-bus controller receives a request from a PCI-bus master to transfer data with an address insecondary memory, the controller performs an initial inquire cycle and withholds TRDY# to the PCI-bus master until any write-back cycle completes. The controller then allows the burst access to take place between secondary memory and the PCI-bus master, and simultaneously and predictively, performs an inquire cycle of the L1 cache for the next cache line. In this manner, if the PCI burst continues past the cache line boundary, the new inquire cycle will already have taken place, or will already be in progress, thereby allowing the burst to proceed with, at most, a short delay. Predictive snoop cycles are not performed if the first transfer of a PCI-bus master access would be the last transfer before a cache line boundary is reached.

Abstract: A system in accordance with the invention provides a chipset for use generally in a PC-type system and that includes a plurality of programmable I/O (PIO) pins. Each of the PIO pins can be programmed to carry signals in accordance with any function in a function pool. In one embodiment, the number of PIO pins total 32 and the number of functions total 70. Such programmability allows a single-chip chipset to be vendor platform-generic while simultaneously minimizing pin count.

Abstract: An I/O interface, compatible with industry standards, for interfacing a host to a peripheral device. The interface includes a clock signal, a bus, an address latch enable signal, a peripheral device ready signal, a command signal, a device selected backoff signal, and a reset signal, resulting in an I/O interface capable of ISA-compatible operation with only 22 pins. Address, data, command, interrupt request, and DMA request information are communicated between the host and the peripheral device via a single bus by multiplexing the information on the bus using phasing techniques.

Abstract: A temperature sensing apparatus is disclosed which generates a signal having a frequency which is related to temperature. The apparatus includes means for receiving a temperature input, an output for carrying an output signal having a frequency related to the temperature output, and a converting means for converting the temperature input to the output signal.

Abstract: A PCI-bus is added to a VESA local bus (VL-bus) computer system using a VL-bus/PCI-bus bridge. The VL-bus/PCI-bus bridge claims a VL-bus cycle by asserting LDEV# to the VL-bus/system-bus bridge. If no other VL-bus device claims the cycle as well, then the VL-bus/PCI-bus bridge translates the cycle onto the PCI-bus and awaits a response from a PCI device. If no PCI device claims a cycle by the PCI-bus device claiming deadline, then the VL-bus/PCI-bus bridge asserts BOFF# to the host and suppresses its assertion of LDEV# when the host repeats the cycle on the VL-bus. The VL-bus/system-bus bridge therefore can translate the repetition of the cycle onto the system bus. When asserting BOFF# to the host, the VL-bus/PCI-bus bridge also asserts the VL-bus device ready signal LRDY# after assertion of BOFF# and releases LRDY# before releasing BOFF#.

Abstract: An I/O interface, compatible with industry standards, for interfacing a host to a peripheral device. The interface includes a clock signal, a bus, an address latch enable signal, a peripheral device ready signal, a command signal, a device selected backoff signal, and a reset signal, resulting in an I/O interface capable of ISA-compatible operation with only 22 pins. Address, data, command, interrupt request, and DMA request information are communicated between the host and the peripheral device via a single bus by multiplexing the information on the bus using phasing techniques.

Abstract: Method and apparatus for improving bus utilization on a bus having a tiered topology, by estimating the worst-case transaction duration time for executing a transaction. The sum of three delays D.sub.fixed, D.sub.data and D.sub.hub.sbsb.--.sub.depth, is detemined, where D.sub.fixed is a delay component which can depend on the transmission duration type of the transaction, as well as other fixed delays; D.sub.data is a delay component which depends on a number N.sub.bytes of bytes to be transmitted for the transaction, and D.sub.hub.sbsb.--.sub.depth is a delay component which depends (in one aspect) on the actual maximum hub depth in the bus topology, or which depends (in another aspect) on the actual hub depth of the target device.

Abstract: A host-bus-to-PCI-bus bridge circuit waits until the PCI-bus clock cycle in which the PCI-bus data transfer corresponding to a current data write access on the originating bus actually takes place, before deciding whether a next data write access is pending on the originating bus and is burstable on the PCI-bus with the current data write access. If so, then the bridge continues the burst with the data of the new data write access. If not, the bridge terminates the PCI-bus burst write transaction by asserting IRDY# and negating FRAME# for the immediately subsequent PCI-bus clock cycle. A final data phase takes place on the PCI-bus in response to these actions, but all data transfer is inhibited because the bridge negates all of the byte-enable signals (BE#(3:0)). An increased likelihood results that successive data write accesses on the originating bus can be collected into a single burst transaction on the PCI-bus.

Abstract: In an IBM PC/AT-compatible computer system, the frequency of the CPU bus clock signal is detected via a hardware apparatus in the I/O interface chipset. The CPU reads the hardware-detected clock frequency from an I/O register. In one embodiment, one bit of the data returned from the register indicates whether the clock frequency indicated by the remainder of the bits is valid. The CPU can trigger the hardware to autodetect the clock frequency by writing arbitrary data to the same address. The hardware clock frequency detection circuitry operates by, in response to a start signal, counting the number of cycles of the CPU clock signal which occur within a predefined number of cycles of the ISA-bus OSC signal. The start signal can be asserted in response negation of the system reset signal, or in response to a write access on the ISA bus to a predefined I/O register, or both.

Abstract: A computer system includes a microprocessor, a cache memory, main memory and supporting logic. The supporting logic includes cache control logic that determines whether an access to memory results in a hit to the cache for dirty or clean data. When a write to the cache results in a hit to clean data, the bus cycle is enlarged in order to set a dirty bit associated with the write data. The bus cycle is enlarged by requesting the processor to refrain from commencing a new bus cycle or driving a new memory address.

Abstract: A system and method in accordance with the invention allows the emulation of a DMA transfer between a device such as a CD-ROM which is incapable of a bus-mastering mode of operation (e.g., a DMA transfer) and a memory. Following receipt of an interrupt request, a system in accordance with the invention generates an I/O access cycle to the device, retrieves data and stores the data in a buffer. Following data retrieval, the system transfers the data to host memory. Once data is transferred to host memory, an interrupt is generated to the host processor. Thus, host processor resources are not required to perform a data transfer with devices unable to become bus-masters.

Abstract: A system in accordance with the invention comprises a first clock input for carrying a clock input signal having first clock cycles, a clock output for carrying an output clock signal having cycles which are synchronous with the first clock cycles, and programmable delay means. Programmable delay means receives the clock input signal, and generates the output clock signal which is delayed from the input by at least a programmable delay and where the programmable delay causes the output clock signal to be synchronous with the input clock signal.

Abstract: A system for writing to a cache memory which eliminates the need, in certain circumstances, to set a dirty bit. The dirty bit indicates that the line of data in the cache has been updated but the corresponding data in main memory has not been updated. Setting the dirty bit can increase the time needed for a bus cycle. When a line of data is written to a cache memory, a dirty bit is set for that line of data. If the next bus cycle is a write to the cache for the same line of data, the cache controller can save time by not setting the dirty bit because the cache controller knows that the dirty bit has been previously set.

Abstract: In a unified memory computer system architecture, the unified memory is divided into at least two banks of memory. All but one of the memory banks is reserved for access exclusively by the host memory controller, and only one bank of memory is shared between the host memory controller and the video controller. Host accesses to the non-shared bank of the unified memory can take place concurrently with video controller accesses to the shared bank of memory.

Abstract: A unified memory architecture includes a dual ported memory, core logic and a serial controller. The dual ported memory contains a random access port and a serial port to support concurrent accesses, after an initial serial port set-up time, through the serial port and the random access port. The core logic handles accesses to the random access port on the dual ported memory for all devices except the serial controller. The serial controller also accesses the dual ported memory through the random access port, and it also receives serial data, for use in a serial data operation, through the serial port. The serial controller generates a serial port load command through the random access port to effectuate the serial data transfer. The serial controller may be a graphics controller that utilizes the dual ported memory as a frame buffer. For this embodiment, the graphics controller executes screen refresh operations through use of the serial port.

Abstract: When a PCI-bus controller receives a request from a PCI-bus master to transfer data with an address in secondary memory, the controller performs an initial inquire cycle and withholds TRDY# to the PCI-bus master until any write-back cycle completes. The controller then allows the burst access to take place between secondary memory and the PCI-bus master, and simultaneously and predictively, performs an inquire cycle of the L1 cache for the next cache line. In this manner, if the PCI burst continues past the cache line boundary, the new inquire cycle will already have taken place, or will already be in progress, thereby allowing the burst to proceed with, at most, a short delay. Predictive snoop cycles are not performed if the first transfer of a PCI-bus master access would be the last transfer before a cache line boundary is reached.

Abstract: Method and apparatus for arbitrating for a shared resource among two or more devices, wherein one device can arbitrate at two or more different levels of priority at different times. Only two conductors are used to communicate between the device and the arbiter: one request signal line and one grant signal line. In order to assert a request for control of memory, the device brings the request signal line to a predefined logic level. The arbiter considers this a low priority request for control of the shared resource, and the arbitration proceeds accordingly. Then, if the device's request is a high priority request, or if it was originally a low priority request and has now become a high priority request, the device brings the request signal to the opposite logic level to thereby increase the priority level of its request. In either case, the arbiter grants control of the shared resource by asserting the device grant signal to the device.

Abstract: A PCI-bus is added to a VESA local bus (VL-bus) computer system using a VL-bus/PCI-bus bridge. The VL-bus/PCI-bus bridge claims a VL-bus cycle by asserting LDEV# to the VL-bus/system-bus bridge. If no other VL-bus device claims the cycle as well, then the VL-bus/PCI-bus bridge translates the cycle onto the PCI-bus and awaits a response from a PCI device. If no PCI device claims a cycle by the PCI-bus device claiming deadline, then the VL-bus/PCI-bus bridge asserts BOFF# to the host and suppresses its assertion of LDEV# when the host repeats the cycle on the VL-bus. The VL-bus/system-bus bridge therefore can translate the repetition of the cycle onto the system bus. When asserting BOFF# to the host, the VL-bus/PCI-bus bridge also asserts the VL-bus device ready signal LRDY# after assertion of BOFF# and releases LRDY# before releasing BOFF#.