Abstract: In a unified memory computer system architecture, the unified memory is divided into at least two banks of memory. All but one of the memory banks is reserved for access exclusively by the host memory controller, and only one bank of memory is shared between the host memory controller and the video controller. Host accesses to the non-shared bank of the unified memory can take place concurrently with video controller accesses to the shared bank of memory.

Abstract: A unified memory architecture includes a dual ported memory, core logic and a serial controller. The dual ported memory contains a random access port and a serial port to support concurrent accesses, after an initial serial port set-up time, through the serial port and the random access port. The core logic handles accesses to the random access port on the dual ported memory for all devices except the serial controller. The serial controller also accesses the dual ported memory through the random access port, and it also receives serial data, for use in a serial data operation, through the serial port. The serial controller generates a serial port load command through the random access port to effectuate the serial data transfer. The serial controller may be a graphics controller that utilizes the dual ported memory as a frame buffer. For this embodiment, the graphics controller executes screen refresh operations through use of the serial port.

Abstract: When a PCI-bus controller receives a request from a PCI-bus master to transfer data with an address in secondary memory, the controller performs an initial inquire cycle and withholds TRDY# to the PCI-bus master until any write-back cycle completes. The controller then allows the burst access to take place between secondary memory and the PCI-bus master, and simultaneously and predictively, performs an inquire cycle of the L1 cache for the next cache line. In this manner, if the PCI burst continues past the cache line boundary, the new inquire cycle will already have taken place, or will already be in progress, thereby allowing the burst to proceed with, at most, a short delay. Predictive snoop cycles are not performed if the first transfer of a PCI-bus master access would be the last transfer before a cache line boundary is reached.

Abstract: Method and apparatus for arbitrating for a shared resource among two or more devices, wherein one device can arbitrate at two or more different levels of priority at different times. Only two conductors are used to communicate between the device and the arbiter: one request signal line and one grant signal line. In order to assert a request for control of memory, the device brings the request signal line to a predefined logic level. The arbiter considers this a low priority request for control of the shared resource, and the arbitration proceeds accordingly. Then, if the device's request is a high priority request, or if it was originally a low priority request and has now become a high priority request, the device brings the request signal to the opposite logic level to thereby increase the priority level of its request. In either case, the arbiter grants control of the shared resource by asserting the device grant signal to the device.

Abstract: A PCI-bus is added to a VESA local bus (VL-bus) computer system using a VL-bus/PCI-bus bridge. The VL-bus/PCI-bus bridge claims a VL-bus cycle by asserting LDEV# to the VL-bus/system-bus bridge. If no other VL-bus device claims the cycle as well, then the VL-bus/PCI-bus bridge translates the cycle onto the PCI-bus and awaits a response from a PCI device. If no PCI device claims a cycle by the PCI-bus device claiming deadline, then the VL-bus/PCI-bus bridge asserts BOFF# to the host and suppresses its assertion of LDEV# when the host repeats the cycle on the VL-bus. The VL-bus/system-bus bridge therefore can translate the repetition of the cycle onto the system bus. When asserting BOFF# to the host, the VL-bus/PCI-bus bridge also asserts the VL-bus device ready signal LRDY# after assertion of BOFF# and releases LRDY# before releasing BOFF#.

Abstract: A memory access chip set includes a data buffer chip and a system controller chip. The data buffer chip contains storage elements that buffer data values transferred between a memory and either the host data bus or the peripheral bus. In one aspect, the storage elements are transparent latches, and not master/slave flip-flops. In another aspect, the storage elements are operated asynchronously. In another aspect, the storage elements are exactly two levels deep (additional accommodations are made in the case of data busses having mismatched widths). The arrangement of storage elements is such that only a single control pin is required on the data buffer chip to enable them, and only a single input pin (plus, in some cases, a clock input pin) for externally coordinating outputs from the storage elements for synchronous transfer over the destination bus.

Abstract: An audio synthesis circuit is disclosed that incorporates a phase accumulator, adder, sinusoid computing circuit, feedback controller, modulation controller and output accumulator. The audio synthesis circuit generates harmonically complex audio tones, which are output from the sinusoid computing circuit via the output accumulator through the use of frequency modulation of the phase of the audio tones. Instead of feeding back the audio tone to modulate the current phase, the disclosed audio synthesis circuit feeds back the current phase, which is converted by the feedback controller into a scaled feedback factor generated through a process using a waveform computing circuit that, without log-linear conversion, computes a preset cyclical function at an argument equal to the current phase. The feedback factor is then added to the current phase to generate a modulated phase value.

Abstract: When a PCI-bus controller receives a request from a PCI-bus master to transfer data with an address in secondary memory, the controller performs an initial inquire cycle and withholds TRDY# to the PCI-bus master until any write-back cycle completes. The controller then allows the burst access to take place between secondary memory and the PCI-bus master, and simultaneously and predictively, performs an inquire cycle of the L1 cache for the next cache line. In this manner, if the PCI burst continues past the cache line boundary, the new inquire cycle will already have taken place, or will already be in progress, thereby allowing the burst to proceed with, at most, a short delay. Predictive snoop cycles are not performed if the first transfer of a PCI-bus master access would be the last transfer before a cache line boundary is reached.

Abstract: An audio synthesis circuit is disclosed that can generate multiple audio tones, or operators, each having different harmonic characteristics. The audio synthesis circuit can be used in a time-multiplexed fashion so that the multiple audio tones, or operators, can be computed in a single audio synthesis cycle and then combined to form voices/channels. Each audio synthesis cycle can be divided into as few as 0 or as many as 48 time slots, meaning that as many as 48 operators can be played simultaneously. The disclosed circuit provides a preset organization of the 48 operators into 12 2-operator channels and 6 4-operator channels. These channels can be played in various system modes, including backward-compatible 2- and 4-operator modes in which the programming of the operators is restricted, and an enhanced mode, in which the operators can be freely programmed. In the backward-compatible modes, two operators of each 4-operator channel are constrained to be duplicates of a respective 2-operator channel.

Abstract: An EISA-compatible computer system having an arbitration mechanism which incorporates a programmable hold delay register and counter for delaying a CPU hold request (DHOLD) by a programmable number of BCLK cycles after an EISA device wins the top level and CPU/EISA level arbitration. The CPU hold request is not delayed if a DMA/ISA device wins the arbitration.

Abstract: A phase-locked loop wherein the output signal is effectively sampled at an increased rate from conventional phase-locked loops, allowing for a greater increase in the ratio of the output frequency to the input frequency while reducing the possibility of jitter or failure to lock. Multiple differently phased reference signals and correspondingly phased feedback signals are produced. The comparison of the feedback signals and the reference signals produce multiple error signals which are combined to adjust the oscillation frequency of the voltage-controlled oscillator.

Abstract: Method and apparatus for reducing the access time required to write to memory and read from memory in a computer system having a cache-based memory. A dynamic determination is made on a cycle by cycle basis of whether data should be written to the cache with a dirty bit asserted, or the data should be written to both the cache and main memory. The write-through method is chosen where the write-through method is approximately as fast as the write-back method. Where the write-back method is substantially faster than the write-through method, the write-back method is chosen.

Abstract: Method and apparatus for reducing the access time required to write to memory and read from memory in a computer system having a cache-based memory. A dynamic determination is made on a cycle by cycle basis of whether data should be written to the cache with a dirty bit asserted, or the data should be written to both the cache and main memory. The write-through method is chosen where the write-through method is approximately as fast as the write-back method. Where the write-back method is substantially faster than the write-through method, the write-back method is chosen.

Abstract: According to the invention, roughly described, the EISA arbitration scheme is used for arbitrating among a plurality of requestors for a system bus, the requestors including the CPU, a refresh controller, EISA devices and ISA/DMA devices. A refresh control signal is asserted if the refresh controller wins the arbitration, and a CAS# before RAS# refresh is performed on local memory in response to the refresh control signal after completion of any CPU access to local memory then taking place. The CPU can continue to access external cache during system bus refresh, and a CPU access to local DRAM is delayed only by the amount of time required for the shorter local DRAM refresh to complete.

Abstract: In a computer system, one or more ISA connector sockets is replaced by a connector structure which carries both ISA signals and local bus signals. The connector structure is arranged such that a standard ISA accessory card may be inserted, in which case only ISA signals are coupled to or from the card. "Local bus" accessory cards may also be designed for insertion into such a connector, and these cards may connect to one or more signal lines of the local bus either additionally or instead of connections made to the ISA bus. By physical or other means, ISA accessory cards are prevented from unintentional contact with connector contacts which are coupled to local bus signal lines. The connector structure may advantageously comprise an EISA-type connector socket.

Abstract: A chipset is provided which permits reading and writing to cache tag memory for testing purposes and for writing non-cacheable tags into tag RAM entries to effectively invalidate the corresponding cache data entries.

Abstract: According to the invention, a chipset is provided which powers up in a default state with caching disabled and which writes permanently non-cacheable tags into tag RAM entries corresponding to memory addresses being read while caching is disabled. Even though no "valid" bit is cleared, erroneous cache hits after caching is enabled are automatically prevented since any address which does match a tag in the tag RAM, is a non-cacheable address and will force retrieval directly from main memory anyway.

Abstract: Several techniques are used to optimize the transmission of signals or events from one bus to the other. In one aspect, the user of a chipset is permitted to choose whether the originating events (i.e. the events in response to which a destination event is to be generated on a destination bus) are to be generated synchronously or asynchronously with the clock signal on the destination bus. Whether synchronous or asynchronous generation is chosen, the chipset may perform a synchronization function in response to an originating bus predictor signal. The number of destination clock cycles to delay before generating the desired destination bus event is responsive to the relative frequencies of the clock signals on the two buses, thereby accommodating a wide variety of such relative frequencies.

Abstract: In an IBM PC AT-compatible computer architecture, CPU-generated addresses and data for accesses to a peripheral device in the I/O address space are coupled directly to the peripheral device from the local bus, without traversing the I/O bus. Any data returned from the peripheral device is coupled directly to the local bus, also without traversing the I/O bus. No buffers are needed for communicating such address and data information between the peripheral device and the I/O bus.

Abstract: According to the invention, a chipset is provided which powers up in a default state with cacheing disabled and which writes permanently non-cacheable tags into tag RAM entries corresponding to memory addresses being read while cacheing is disabled. Even though no "valid" bit is cleared, erroneous cache hits after cacheing is enabled are automatically prevented since any address which does match a tag in the tag RAM, is a non-cacheable address and will force retrieval directly from main memory anyway. Two cache tag test modes are also described, as is a cache sizing algorithm.