Abstract: A method includes receiving, from a system manufacturer, system test data for a plurality of electronic systems. Each of the plurality of electronic systems includes a plurality of electronic components. The method also includes determining a relationship between a set of electronic components from the plurality of electronic components and the electronic systems upon which the electronic components of the set of electronic components are assembled and receiving, from a component manufacturer, manufacturing attributes for the set of electronic components. The method further includes selecting a data subset from the system test data corresponding to a subgroup of the set of electronic components. The subgroup includes components from a same fabrication cluster. Additionally, the method includes identifying an outlier relative to the data subset and communicating information about the outlier to at least one of the system manufacturer or the component manufacturer.

Abstract: A method includes receiving system test data for a plurality of electronic systems. Each of the electronic systems includes a plurality of electronic components. The method also includes determining a relationship between a set of electronic components and the electronic systems upon which the electronic components of the set of electronic components are assembled and receiving manufacturing attributes including spatial data for the set of electronic components. The method further includes selecting a data subset from the system test data corresponding to a subgroup of the set of electronic components. The subgroup includes components within an area defined on a substrate according to a spatial pattern and that is fewer than all of the set of electronic components on the substrate. Additionally, the method includes identifying an outlier relative to the data subset and communicating information about the outlier to at least one of a system or a component manufacturer.

Abstract: Systems and methods for sorting an electronic device undergoing a final test operation in accordance with a test program, into one of a plurality of bins. In one embodiment, an evaluator defines the binning of the electronic device while the device is still socketed, and the defined binning may or may not concur with the binning assigned by the test program.

Abstract: A method for modifying the execution sequence of tests for testing an object on a test system. The tests include a group of tests that is a candidate for replacement. The method includes: while executing the tests according to the execution sequence and before executing the group of tests, modifying, in real time, the execution sequence including: executing a delay instead of the group of tests, wherein the delay is related to the group of tests.

Abstract: Disclosed are methods, systems and computer program products where an item may or may not be determined as counterfeit based on result(s) of a comparison between test data for the item, and test data for items that are associated with manufacturing data in the cluster that is most likely to include manufacturing data that is associated with attribute data obtained for the item. In some embodiments, such methods, systems and computer program products may allow automated, universal non-destructive, and/or non-invasive detection of counterfeit electronic items. In some embodiments, counterfeit detection may be integrated into existing supply chains, including high volume manufacturing supply chains, and may be performed for a large variety of items without a need for a major adjustment to manufacturing. However, the counterfeit detection in some embodiments may not necessarily be integrated into manufacturing and may occur at any time, even when an item is in use.

Abstract: Methods and systems for semiconductor testing are disclosed. In one embodiment, devices which are testing too slowly are prevented from completing testing, thereby allowing untested devices to begin testing sooner.

Abstract: Methods and systems for semiconductor testing are disclosed. In one embodiment, devices which are testing too slowly are prevented from completing testing, thereby allowing untested devices to begin testing sooner.

Abstract: Systems and methods for deciding whether or not to indicate misalignment. In some examples, an analysis of parametric data relating to tests sensitive to misalignment is performed in order to determine which data is incongruous and to identify corresponding probes or socket contacts as suspected misaligned. In some examples, additionally or alternatively, a spatial analysis quantifies the placement of a set of identified suspected misaligned probes, which were identified from pass/fail test data and/or parametric test data, with respect to a contiguous or non-contiguous area on one or more wafers.

Abstract: Methods, systems, computer-program products and program-storage devices for determining whether or not to perform an action based at least partly on an estimated maximum test-range. One method comprises: attaining results generated from a parametric test on semiconductor devices included in a control set; selecting from the semiconductor devices at least one extreme subset including at least one of a high-scoring subset and a low-scoring subset; plotting at least results of the at least one extreme subset; fitting a plurality of curves to a plurality of subsets of the results; extending the curves to the zero-probability axis for the low-scoring subset or the one-probability axis for the high-scoring subset to define a corresponding plurality of intersection points; defining an estimated maximum test range based on at least one of the intersection points; and determining whether or not to perform an action based at least partly on the estimated maximum test range.