Patents Assigned to Optimaltest Ltd.
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Publication number: 20130193994Abstract: Methods and systems for semiconductor testing are disclosed. In one embodiment, devices which are testing too slowly are prevented from completing testing, thereby allowing untested devices to begin testing sooner.Type: ApplicationFiled: March 14, 2013Publication date: August 1, 2013Applicant: OptimalTest, Ltd.Inventor: OptimalTest, Ltd.
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Patent number: 8421494Abstract: Methods and systems for semiconductor testing are disclosed. In one embodiment, devices which are testing too slowly are prevented from completing testing, thereby allowing untested devices to begin testing sooner.Type: GrantFiled: May 23, 2011Date of Patent: April 16, 2013Assignee: OptimalTest Ltd.Inventors: Gil Balog, Reed Linde, Avi Golan
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Publication number: 20120123734Abstract: Systems and methods for deciding whether or not to indicate misalignment. In some examples, an analysis of parametric data relating to tests sensitive to misalignment is performed in order to determine which data is incongruous and to identify corresponding probes or socket contacts as suspected misaligned. In some examples, additionally or alternatively, a spatial analysis quantifies the placement of a set of identified suspected misaligned probes, which were identified from pass/fail test data and/or parametric test data, with respect to a contiguous or non-contiguous area on one or more wafers.Type: ApplicationFiled: November 11, 2010Publication date: May 17, 2012Applicant: OPTIMALTEST LTD.Inventors: Reed LINDE, Dan GLOTTER, Alexander CHUFAROVSKY, Leonid GUROV
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Publication number: 20120109874Abstract: Methods and systems for semiconductor testing. In one embodiment, a semiconductor testing method includes one or more of the following stages: defining a rule relating to semiconductor testing, validating the rule, bundling the rule with other rules, correlating the rule with other rules, publishing the rule, actualizing the rule, and follow up relating to the rule. In one embodiment, a semiconductor testing system includes one or more of the following modules: rule creation module(s), analysis module(s), simulation module(s), real time production module(s), and offline production module(s). In one embodiment, user friendly graphical user interface(s) can be used for defining the building blocks of a rule and/or for viewing an optional hierarchy of categories to which the rule belongs.Type: ApplicationFiled: October 18, 2011Publication date: May 3, 2012Applicant: OptimalTest Ltd.Inventor: Gil Balog
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Patent number: 8112249Abstract: A parametric test time reduction method for reducing time expended to conduct a test program flow on a population of semiconductor devices, the test program flow comprising at least one parametric test having a specification defining a known pass value range characterized in that a result of the test is considered a passing result if the result falls within the known pass value range, the method including: computing an estimated maximum test range, at a given confidence level, on a validation set including a subset of the population of semiconductor devices, the estimated maximum test range including the range of values into which all results from performing the test on the set will statistically fall at the given confidence level and at least partly disabling the at least one parametric test based at least partly on a comparison of the estimated maximum test range and the known pass value range.Type: GrantFiled: December 22, 2008Date of Patent: February 7, 2012Assignee: Optimaltest Ltd.Inventors: Leonid Gurov, Alexander Chufarovsky, Gil Balog
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Patent number: 8069130Abstract: Methods and systems for semiconductor testing. In one embodiment, a semiconductor testing method includes one or more of the following stages: defining a rule relating to semiconductor testing, validating the rule, bundling the rule with other rules, correlating the rule with other rules, publishing the rule, actualizing the rule, and follow up relating to the rule. In one embodiment, a semiconductor testing system includes one or more of the following modules: rule creation module(s), analysis module(s), simulation module(s), real time production module(s), and offline production module(s). In one embodiment, user friendly graphical user interface(s) can be used for defining the building blocks of a rule and/or for viewing an optional hierarchy of categories to which the rule belongs.Type: GrantFiled: June 29, 2009Date of Patent: November 29, 2011Assignee: Optimaltest Ltd.Inventor: Gil Balog
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Publication number: 20110251812Abstract: Methods, systems, computer program products and program storage devices for determining whether or not to perform an action based at least partly on an estimated maximum test range.Type: ApplicationFiled: June 21, 2011Publication date: October 13, 2011Applicant: OPTIMALTEST LTD.Inventors: Leonid GUROV, Alexander CHUFAROVSKY, Gil BALOG, Reed LINDE
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Publication number: 20110224938Abstract: Methods and systems for semiconductor testing are disclosed. In one embodiment, devices which are testing too slowly are prevented from completing testing, thereby allowing untested devices to begin testing sooner.Type: ApplicationFiled: May 23, 2011Publication date: September 15, 2011Applicant: OptimalTest Ltd.Inventors: Gil Balog, Reed Linde, Avi Golan
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Patent number: 7969174Abstract: Methods and systems for semiconductor testing are disclosed. In one embodiment, devices which are testing too slowly are prevented from completing testing, thereby allowing untested devices to begin testing sooner.Type: GrantFiled: April 3, 2009Date of Patent: June 28, 2011Assignee: OptimalTest Ltd.Inventors: Gil Balog, Reed Linde, Avi Golan
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Publication number: 20110000829Abstract: Systems and methods for sorting an electronic device undergoing a final test operation in accordance with a test program, into one of a plurality of bins. In one embodiment, an evaluator defines the binning of the electronic device while the device is still socketed, and the defined binning may or may not concur with the binning assigned by the test program.Type: ApplicationFiled: July 6, 2009Publication date: January 6, 2011Applicant: OptimalTest Ltd.Inventors: Reed Linde, Gill Balog
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Patent number: 7777515Abstract: Methods and systems of semiconductor testing where reference dice and non-reference dice in a wafer and/or lot are tested differently. In one embodiment of the invention, geography, lithography exposure, other characteristics, performance and/or behavior are taken into account when selecting reference dice, thereby improving the likelihood that the response of reference dice to testing is well representative of the wafer and/or lot. In one embodiment, based on data from the testing of reference dice, the test flow for non-reference dice and/or other testing may or may not be adjusted.Type: GrantFiled: December 30, 2008Date of Patent: August 17, 2010Assignee: OptimalTest Ltd.Inventor: Gil Balog
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Publication number: 20100161276Abstract: A parametric test time reduction method for reducing time expended to conduct a test program flow on a population of semiconductor devices, the test program flow comprising at least one parametric test having a specification which defines a known pass value range characterized in that a result of the test is considered a passing result if the result falls within the known pass value range, the method comprising, for at least one parametric test, computing an estimated maximum test range, at a given confidence level, on a validation set comprising a subset of the population of semiconductor devices, the estimated maximum test range comprising the range of values into which all results from performing the test on the set will statistically fall at the given confidence level, the validation set defining a complementary set including all semiconductors included in the population and not included in the validation set; and at least partly disabling the at least one parametric test based at least partly on a comparType: ApplicationFiled: December 22, 2008Publication date: June 24, 2010Applicant: OptimalTest Ltd.Inventors: Leonid Gurov, Alexander Chufarovsky, Gil Balog
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Patent number: 7737716Abstract: Methods and systems of semiconductor testing where reference dice and non-reference dice in a wafer and/or lot are tested differently. In one embodiment of the invention, geography, lithography exposure, other characteristics, performance and/or behavior are taken into account when selecting reference dice, thereby improving the likelihood that the response of reference dice to testing is well representative of the wafer and/or lot. In one embodiment, based on data from the testing of reference dice, the test flow for non-reference dice and/or other testing may or may not be adjusted.Type: GrantFiled: December 30, 2008Date of Patent: June 15, 2010Assignee: OptimalTest Ltd.Inventor: Gil Balog
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Patent number: 7679392Abstract: Methods and systems of semiconductor testing where reference dice and non-reference dice in a wafer and/or lot are tested differently. In one embodiment of the invention, geography, lithography exposure, other characteristics, performance and/or behavior are taken into account when selecting reference dice, thereby improving the likelihood that the response of reference dice to testing is well representative of the wafer and/or lot. In one embodiment, based on data from the testing of reference dice, the test flow for non-reference dice and/or other testing may or may not be adjusted.Type: GrantFiled: December 30, 2008Date of Patent: March 16, 2010Assignee: OptimalTest Ltd.Inventor: Gil Balog
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Publication number: 20090265300Abstract: Methods and systems for semiconductor testing. In one embodiment, a semiconductor testing method includes one or more of the following stages: defining a rule relating to semiconductor testing, validating the rule, bundling the rule with other rules, correlating the rule with other rules, publishing the rule, actualizing the rule, and follow up relating to the rule. In one embodiment, a semiconductor testing system includes one or more of the following modules: rule creation module(s), analysis module(s), simulation module(s), real time production module(s), and offline production module(s). In one embodiment, user friendly graphical user interface(s) can be used for defining the building blocks of a rule and/or for viewing an optional hierarchy of categories to which the rule belongs.Type: ApplicationFiled: June 29, 2009Publication date: October 22, 2009Applicant: OptimalTest Ltd.Inventor: Gil Balog
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Publication number: 20090192754Abstract: Methods and systems for semiconductor testing are disclosed. In one embodiment, devices which are testing too slowly are prevented from completing testing, thereby allowing untested devices to begin testing sooner.Type: ApplicationFiled: April 3, 2009Publication date: July 30, 2009Applicant: OptimalTest Ltd.Inventors: Gil Balog, Reed Linde, Avi Golan
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Patent number: 7567947Abstract: Methods and systems for semiconductor testing. In one embodiment, a semiconductor testing method includes one or more of the following stages: defining a rule relating to semiconductor testing, validating the rule, bundling the rule with other rules, correlating the rule with other rules, publishing the rule, actualizing the rule, and follow up relating to the rule. In one embodiment, a semiconductor testing system includes one or more of the following modules: rule creation module(s), analysis module(s), simulation module(s), real time production module(s), and offline production module(s). In one embodiment, user friendly graphical user interface(s) can be used for defining the building blocks of a rule and/or for viewing an optional hierarchy of categories to which the rule belongs.Type: GrantFiled: April 4, 2006Date of Patent: July 28, 2009Assignee: Optimaltest Ltd.Inventor: Gil Balog
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Patent number: 7532024Abstract: Methods and systems of semiconductor testing where reference dice and non-reference dice in a wafer and/or lot are tested differently. In one embodiment of the invention, geography, lithography exposure, other characteristics, performance and/or behavior are taken into account when selecting reference dice, thereby improving the likelihood that the response of reference dice to testing is well representative of the wafer and/or lot. In one embodiment, based on data from the testing of reference dice, the test flow for non-reference dice and/or other testing may or may not be adjusted.Type: GrantFiled: July 5, 2006Date of Patent: May 12, 2009Assignee: Optimaltest Ltd.Inventor: Gil Balog
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Publication number: 20090115445Abstract: Methods and systems of semiconductor testing where reference dice and non-reference dice in a wafer and/or lot are tested differently. In one embodiment of the invention, geography, lithography exposure, other characteristics, performance and/or behavior are taken into account when selecting reference dice, thereby improving the likelihood that the response of reference dice to testing is well representative of the wafer and/or lot. In one embodiment, based on data from the testing of reference dice, the test flow for non-reference dice and/or other testing may or may not be adjusted.Type: ApplicationFiled: December 30, 2008Publication date: May 7, 2009Applicant: OptimalTest Ltd.Inventor: Gil Balog
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Publication number: 20090119048Abstract: Methods and systems of semiconductor testing where reference dice and non-reference dice in a wafer and/or lot are tested differently. In one embodiment of the invention, geography, lithography exposure, other characteristics, performance and/or behavior are taken into account when selecting reference dice, thereby improving the likelihood that the response of reference dice to testing is well representative of the wafer and/or lot. In one embodiment, based on data from the testing of reference dice, the test flow for non-reference dice and/or other testing may or may not be adjusted.Type: ApplicationFiled: December 30, 2008Publication date: May 7, 2009Applicant: OptimalTest Ltd.Inventor: Gil Balog