Abstract: Methods and systems of semiconductor testing where reference dice and non-reference dice in a wafer and/or lot are tested differently. In one embodiment of the invention, geography, lithography exposure, other characteristics, performance and/or behavior are taken into account when selecting reference dice, thereby improving the likelihood that the response of reference dice to testing is well representative of the wafer and/or lot. In one embodiment, based on data from the testing of reference dice, the test flow for non-reference dice and/or other testing may or may not be adjusted.

Abstract: A method for augmenting quality or reliability of semiconductor units, including providing few populations of semiconductor units that are subject to quality or reliability testing. The populations include few quality or reliability fail candidate populations and other population(s). The method includes the step of associating test flows to the populations. Each test flow includes stress testing sequence. The stress testing sequence for the quality or reliability fail candidate population includes a stress test of increased duration compared to duration of a stress test in the test flow of the other population. The stress test sequence for the other population includes a stress test of increased voltage compared to corresponding operating voltage specification for a semiconductor unit. The method further includes the step of applying, within a sort testing stage, the corresponding test flow to the populations and identifying any unit which failed the stress sequence.

Abstract: Methods and systems of semiconductor testing where reference dice and non-reference dice in a wafer and/or lot are tested differently. In one embodiment of the invention, geography, lithography exposure, other characteristics, performance and/or behavior are taken into account when selecting reference dice, thereby improving the likelihood that the response of reference dice to testing is well representative of the wafer and/or lot. In one embodiment, based on data from the testing of reference dice, the test flow for non-reference dice and/or other testing may or may not be adjusted.

Abstract: Parallel dies testing, mostly implemented on memory ICs—Integrated Circuits, significantly reduced overall test time. In order to minimize the need for physical probing, wafer probe card technology to allow simultaneous probing, ATE—Automated Test Equipment with enough channels and CPU power to handle the parallel testing. While new devices are designed with enough channels, and probe cards are designed and manufactured for each new device, the need to purchase new ATE to benefit from the technology is a heavy burden on parallel testing. It is proposed to interpose a multiplexer between the probe card and the ATE accompanied by a system that optimizes tester resources. The proposed system will allow test houses to benefit most from their investment without paying the full penalty of keeping less capable ATE.

Abstract: Parallel dies testing, mostly implemented on memory ICs—Integrated Circuits, significantly reduced overall test time. In order to minimize the need for physical probing, wafer probe card technology to allow simultaneous probing, ATE—Automated Test Equipment with enough channels and CPU power to handle the parallel testing. While new devices are designed with enough channels, and probe cards are designed and manufactured for each new device, the need to purchase new ATE to benefit from the technology is a heavy burden on parallel testing. It is proposed to interpose a multiplexer between the probe card and the ATE accompanied by a system that optimizes tester resources. The proposed system will allow test houses to benefit most from their investment without paying the full penalty of keeping less capable ATE.