Patents Assigned to OPTIS CIRCUIT TECHNOLOGY, LLC
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Patent number: 9847901Abstract: A method and an apparatus determine a time of start of series of OFDM symbols forming an OFDM packet, wherein one or more symbols of the OFDM signal includes a plurality of copies of a short training sequence made of a plurality of time-domain samples. The method includes determining a coarse time index, determining a fine time index, and determining the time of start of each OFDM symbols based on the fine time index. The coarse time-domain sample of the coarse time index is within a coarse estimation error interval, and the time-domain samples of the coarse estimation error interval are converted into frequency domain samples. A metric value is determined for each frequency domain samples, and the fine time index is the time index corresponding to one of the coarse estimation error interval having its associated frequency domain sample having the lowest metric value.Type: GrantFiled: November 25, 2013Date of Patent: December 19, 2017Assignee: OPTIS CIRCUIT TECHNOLOGY, LLCInventor: Achraf Dhayni
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Patent number: 9810584Abstract: A temperature sensor includes two branches, each branch having at least a first transistor and a second transistor connected as diodes and cascaded, so that an emitter of the first transistor is connected to a collector of the second transistor of the same branch. The temperature source also includes a current source configured to provide a current to the two branches, and an analog-to-digital convertor. The analog-to-digital convertor is connected to capture a voltage between emitters of the first transistors or of the second transistors, and is configured to convert said voltage to a digital temperature signal.Type: GrantFiled: February 10, 2014Date of Patent: November 7, 2017Assignee: OPTIS CIRCUIT TECHNOLOGY, LLCInventors: Jukka Kohola, Marko Pessa
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Patent number: 9781439Abstract: A method of encoding video data including a sequence of digital image frames, in a pipelined processing system is provided. The method includes dividing each frame in the sequence into a plurality of sections, each section including a horizontal band across a frame. The method further includes subdividing each section into a plurality of macroblocks, and encoding a representation of each macroblock in each section to form an output stream. The sections of each frame are processed during adjacent steps in a pipeline of the pipelined processing system.Type: GrantFiled: January 28, 2014Date of Patent: October 3, 2017Assignee: OPTIS CIRCUIT TECHNOLOGY, LLCInventors: Valerie Pierson, Vincent Migeotte
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Patent number: 9779482Abstract: A method allows changing an image raster direction from an application raster direction to a screen raster direction, in-flight while pixel values of an image are transferred successively from an application output memory to a display unit. A single buffer memory array is implemented between the application output memory and the display unit. Two writing orders for cells of the buffer memory array are used in turn, each being combined with a different reading order for the cells. The method can be hardware-implemented, and is adapted for burst-handling of the pixel values.Type: GrantFiled: April 14, 2014Date of Patent: October 3, 2017Assignee: OPTIS CIRCUIT TECHNOLOGY, LLCInventor: Gilles Ries
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Patent number: 9720470Abstract: The present invention relates to a method for controlling the operation of an electronic device for processing data, said device comprising at least one computational unit for receiving input data and processing said input data for generating output data, and further comprising a control unit for receiving at least a part of said input data and delivering at least one control signal to said at least one computational unit for controlling the operation of said at least one computational unit, characterized in said control unit using said input data to determine a computational effort and further using said control signal to control parameters of said at least one computational unit depending on said computational effort, wherein said parameters comprise a combination of: clock rate and/or supply voltage; and process complexity.Type: GrantFiled: May 9, 2011Date of Patent: August 1, 2017Assignee: OPTIS CIRCUIT TECHNOLOGY, LLCInventors: Erik G. Larsson, Oscar Gustafsson
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Patent number: 9716383Abstract: A system for delivering a voltage to at least one power domain has at least one component. Each power domain functions according to at least two operating points, each operating point requiring a distinct supply voltage. The system includes at least two power supply units, alternatively delivering controllable supply voltages. The system also includes a control unit that selects one of the power supply units to be connected to a power domain, based on a current operating point of the power domain. The control unit also controls the supply voltage delivered by the selected power supply unit, to deliver the required voltage level associated with the current operating point of the power domain.Type: GrantFiled: October 15, 2012Date of Patent: July 25, 2017Assignee: OPTIS CIRCUIT TECHNOLOGY, LLCInventors: Laurent Meunier, Anders Carlsson, Tomas Olsson
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Absolute value current-sensing circuit for step-down DC-to-DC converters with integrated power stage
Patent number: 9709608Abstract: A system for measuring an output current of a DC-to-DC converter with a transistor power stage includes a voltage measuring circuit and an impedance. The voltage measuring circuit, which is connected to the output of the power stage of the DC-to-DC converter, measures an average voltage drop on impedances of the transistors of the power stage. The impedance, which is connected to an output of the voltage measuring circuit, reproduces the impedances of the transistors of the power stage and is traversed by a scaled version of the current output of the voltage measuring circuit.Type: GrantFiled: May 8, 2015Date of Patent: July 18, 2017Assignee: OPTIS CIRCUIT TECHNOLOGY, LLCInventor: Vratislav Michal -
Patent number: 9705400Abstract: An output stage configuration with four configurable input/output terminals and four switches is specified. Each switch has a first main terminal, a second main terminal and a control terminal, which receives a control signal for controlling the open or closed state of the switch. The output stage is included in a circuit together with a first control apparatus and a second control apparatus. When a control stage of the first control apparatus is connected to the output stage, a control stage of the second control apparatus is electrically disconnected from the output stage, and the output stage operates in a first operating state. When the control stage of the second control apparatus is connected to the output stage, the control stage of the first control apparatus is electrically disconnected from the output stage, the output stage then operating in a second operating state.Type: GrantFiled: June 2, 2014Date of Patent: July 11, 2017Assignee: OPTIS CIRCUIT TECHNOLOGY, LLCInventors: Philippe Sirito-Olivier, Patrizia Milazzo, Angelo Nagari
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Patent number: 9679145Abstract: The present invention relates to a method of managing switching from a first mode of operation to a second mode of operation a first processor in a processing device which comprises at least one other processor and a controller processor. The method comprises receiving a message which comprises a request to switch the first processor from a first to a second mode of operation; deciding whether the switching is appropriate; and upon decision of switching, switching the first processor from a first mode of operation to a second mode of operation according to the selected type of switching.Type: GrantFiled: October 4, 2012Date of Patent: June 13, 2017Assignee: OPTIS CIRCUIT TECHNOLOGY, LLCInventors: Gilles Gallet, Julie Gonin, Nicolas Mareau, Claire Verilhac
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Patent number: 9645837Abstract: A method in a Just-In-Time, JIT, compiler for compiling code in a JIT-compiler for a heterogeneous multiprocessor system is provided. The method comprises compiling a snippet of input code, whereby one or more compiled code snippets are generated for the snippet of input code. The one or more compiled code snippets are tagged with one or more snippet specific characteristics. One or more compiled code snippets are selected from the compiled code snippets, based on said snippet specific characteristics. The one or more selected compiled code snippets are executed on one or more of the plurality of processors. While executing, run-time data is gathered, where the gathered data is tagged for which processor in the heterogeneous multiprocessor system it is related to.Type: GrantFiled: October 25, 2013Date of Patent: May 9, 2017Assignee: OPTIS CIRCUIT TECHNOLOGY, LLCInventor: Andreas Anyuru
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Patent number: 9641362Abstract: A receiver for an N-wire digital interface, where N is any integer exceeding two, has N input terminals, a common node and N detection stages. Each of the N detection stages has a resistive element coupled between the common node and a respective one of the N input terminals, and a comparator having a first input coupled to the respective one of the N input terminals and a second input coupled to the common node.Type: GrantFiled: June 17, 2014Date of Patent: May 2, 2017Assignee: OPTIS CIRCUIT TECHNOLOGY, LLCInventor: Kimmo Koli
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Patent number: 9628906Abstract: An electrical interface circuit includes a microphone circuit, a battery charger circuit and an electrical connector for connecting the electrical interface circuit to an external device. The electrical connector has a pin on which signals are multiplexed for connecting either the battery charger circuit to an external supply voltage, or the microphone circuit to an external microphone. The battery charger circuit includes an amplifying circuit for controlling voltage or current to a battery at battery charging, and a p-type power transistor. The pin is connected to the microphone circuit and to a source of the p-type power transistor. When a voltage applied to the pin exceeds the battery voltage, the p-type power transistor provides current from the pin to the charger circuit, and, otherwise, the charger circuit and battery are disconnected from the pin. A method of multiplexing signals on the electrical interface circuit is also disclosed.Type: GrantFiled: February 9, 2012Date of Patent: April 18, 2017Assignee: OPTIS CIRCUIT TECHNOLOGY, LLCInventors: Gajendranath Chowdary, Ravpreet Singh, Shyam Somayajula
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Patent number: 9627879Abstract: An apparatus (100) for protecting a circuit (200) from an input volume comprises a switchable element (10) arranged to couple the input voltage (VIN) to the circuit (200) in response to a first control signal (DRV1) having a first value and to decouple the input voltage (VIN) from the circuit (200) in response to the first control signal (DRV1) having a second value. A monitor stage (20) compares a monitored voltage (VMON) to a threshold (VIN). A controller (30) provides the first control signal (DRV1) to the switchable element (10), the first control signal (DRV1) having the first value when the monitored voltage (VMON) is on one side of the threshold (VTH) and the second value when the monitored voltage (VMON) is on the other side of the threshold (VTH), wherein the first value is independent of the input voltage (VIN) and the second value is equal to the input voltage (VIN).Type: GrantFiled: December 2, 2011Date of Patent: April 18, 2017Assignee: OPTIS CIRCUIT TECHNOLOGY, LLCInventors: Marco Zamprogno, Alberto Minuti, Germano Nicollini
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Patent number: 9629157Abstract: A method of controlling a frequency selection of a PLL used in cooperation with a device of a wireless communication network, such as a Universal Mobile Telecommunication System (UMTS) network, the method comprising: —receiving a first set of signal measurements; —comparing the first set of signal measurements with a first threshold and, selectively switching the PLL frequency from a first value to a second value as a result of the comparison of the first set of signal measurements with the first threshold; —further receiving a second set of signal measurements; and, —comparing the second set of signal measurements with a second threshold, different from the first threshold, and selectively switching the PLL frequency from the second value to the first value as a result of the comparison of the second set of signal measurements with the second threshold.Type: GrantFiled: February 11, 2013Date of Patent: April 18, 2017Assignee: OPTIS CIRCUIT TECHNOLOGY, LLCInventors: Pierre Demaj, Fabrizio Tomatis
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Patent number: 9602764Abstract: The present invention discloses a method for implementing a video phone on a communication terminal, and the communication terminal thereof. The method comprises the steps of: determining, by the communication terminal, that it supports video phone services and is located in a second communication access network which supports the transmission of a second data contained in the video phone services; initiating or waiting for a video phone call; establishing and maintaining a video phone connection with a second communication terminal; and switching CS domain services to a first communication access network which supports the transmission of a first data contained in the CS domain services after the video phone connection is terminated.Type: GrantFiled: January 16, 2012Date of Patent: March 21, 2017Assignee: OPTIS CIRCUIT TECHNOLOGY, LLCInventors: Hongping Song, Chao Gong
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Patent number: 9602059Abstract: An amplifier has an input port for receiving an input signal and an envelope port for receiving an envelope signal indicative of an envelope of the input signal, and an output port for delivering an amplified signal. The amplifier has a first transistor and a second transistor. A first biasing circuit is coupled to the envelope port and is arranged to generate a first bias voltage dependent on the envelope signal. A summing stage is coupled to the input port for receiving the input signal, to the first biasing circuit for receiving the first bias voltage, and to the gate of the first transistor. A second biasing circuit is coupled between the envelope port and the gate of the second transistor, and is arranged to generate a second bias voltage dependent on the envelope signal.Type: GrantFiled: March 20, 2014Date of Patent: March 21, 2017Assignee: OPTIS CIRCUIT TECHNOLOGY, LLCInventor: Vincent Knopik
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Patent number: 9591284Abstract: A method of indicating a suitable pose for a camera for obtaining a stereoscopic image, with the camera comprising an imaging sensor. The method comprises obtaining and storing a first image of a scene using the imaging sensor when the camera is in a first pose; moving the camera to a second pose; and obtaining a second image of the scene when the camera is in the second pose. One or more disparity vectors are determined, each disparity vector being determined between a feature identified within the first image and a corresponding feature identified in the second image. On the basis of the one or more disparity vectors, a determination is made of whether the second image of the scene is suitable for use, together with the first image, as a stereoscopic image pair.Type: GrantFiled: December 23, 2013Date of Patent: March 7, 2017Assignee: OPTIS CIRCUIT TECHNOLOGY, LLCInventor: Stéphane Valente
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Patent number: 9591620Abstract: A method permits a UE receiver to detect and report to the network a scrambling code collision (i.e., two neighbor cells transmitting with the same scrambling code while timing is aligned). The UE receiver decodes the PCCPCH's physical channel with all the associated broadcast information while a scrambling code collision at the UE is present. The UE reports SFN-SFN information to the network, to insure the UE mobility and then prepare the handover to a new detected cell. This process and a respective apparatus are usable in the presence of MIMO and further improve the detection of the scrambling code collision in the presence of MIMO.Type: GrantFiled: June 21, 2013Date of Patent: March 7, 2017Assignee: OPTIS CIRCUIT TECHNOLOGY, LLCInventors: Fabrizio Tomatis, Andrea Ancora
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Patent number: 9590689Abstract: An RF front end circuit has a common impedance matching network connected to an output terminal, a first power amplifier arranged to drive power to the output terminal through the common impedance matching network, a second power amplifier adapted to drive power to the output terminal through the common impedance matching network, a second impedance matching network, and a reference terminal at a reference voltage. The second impedance matching network has at least a first connection path to the reference terminal, a second connection path to the second power amplifier and a third connection path to the common impedance matching network. The second impedance matching network also includes a first impedance switch configured to open the first connection path responsive to the second power amplifier being put into an OFF state.Type: GrantFiled: October 17, 2012Date of Patent: March 7, 2017Assignee: OPTIS CIRCUIT TECHNOLOGY, LLCInventor: Vincent Knopik
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Patent number: 9577769Abstract: An OFDM communication transceiver, which is configured to test its connection with an antenna circuit unit, has a receiver chain and an emitting chain. The receiver chain includes a time-to-frequency transform unit and the emitting chain includes a frequency-to-time transform unit. The transceiver further includes means for disconnecting the receiver chain to the antenna circuit unit, means for providing a stimulus as input to the emitting chain, means for reintroducing the signal at the output of the emitting chain as an input of the receiving chain, means for determining a circuit resonance frequency, Fr, and a quality factor, Q, of a transfer function computed from the output of the time-to-frequency transform unit, and means for deciding about the connection of said antenna circuit unit according to the resonance frequency and the quality factor.Type: GrantFiled: July 31, 2013Date of Patent: February 21, 2017Assignee: OPTIS CIRCUIT TECHNOLOGY, LLCInventor: Achraf Dhayni