Abstract: In an embodiment, a method for producing optoelectronic semiconductor devices includes applying a temporal spacer to protect a light-exit face of an optoelectronic semiconductor chip by applying a photoresist onto a first carrier, subsequently developing the photoresist in places thereby forming the temporal spacer and subsequently mounting the optoelectronic semiconductor chip onto a side of the temporal spacer facing away from the first carrier, forming a reflector in a lateral direction directly around the optoelectronic semiconductor chip and around the temporal spacer, subsequently removing the temporal spacer so that the reflector extends beyond the light-exit face and applying an optical element onto the reflector so that a gap exists between the light-exit face and a light-entrance face of the optical element.
Type:
Grant
Filed:
March 8, 2019
Date of Patent:
May 21, 2024
Assignee:
OSRAM Opto Semiconductors GmbH
Inventors:
Choo Kean Lim, Xiao Fen Hoo, Wan Leng Lim, Ai Cheng Chan
Abstract: An optoelectronic semiconductor device may include a first semiconductor layer and a second semiconductor layer, the first and second semiconductor layers being stacked one above the other. The device may include a first contact structure and a contact layer. The device may include a separating layer arranged over a side of the contact layer, and a current spreading layer arranged over a side of the separating layer facing away from the contact layer. The first contact structure may be connected to the contact layer via the current spreading layer and the separating layer. A layer stack may include the contact layer, the separating layer, and the current spreading layer has an anisotropic conductivity. The separating layer is present as a continuous layer in a region between the contact layer and the current spreading layer.
Abstract: A method for operating a light emitting diode arrangement with at least one light emitting diode includes the steps of: a) determining at least one instantaneous current-voltage value pair; b) matching the instantaneous current-voltage value pair with an original current-voltage value pair; and c) determining an updated current feed based on the matching and driving the light emitting diode with the updated current feed.
Type:
Grant
Filed:
June 4, 2020
Date of Patent:
May 14, 2024
Assignee:
OSRAM Opto Semiconductors GmbH
Inventors:
Michael Binder, Holger Specht, Maximilian Tauer
Abstract: A multi-pixel display device with an integrated circuit, a plurality of light-emitting semiconductor chips disposed on the integrated circuit, a display area having a plurality of pixels, each of the light-emitting semiconductor chips being associated with one of the pixels, a light-directing element disposed between the plurality of light-emitting semiconductor chips and the display area and adapted to direct the light of each light-emitting semiconductor chip from the plurality of light-emitting semiconductor chips to its associated pixel.
Abstract: The invention relates to an optoelectronic component, comprising: at least two optoelectronic semiconductor chips, which are designed to emit electromagnetic radiation during operation; at least one connecting element, which is electrically conductive, flexible and extensible; and a shaped body, which surrounds the at least two optoelectronic semiconductor chips and the at least one connecting element at least in some locations, wherein the optoelectronic semiconductor chips are each arranged on a carrier. The invention further relates to a method for producing an optoelectronic component.
Type:
Grant
Filed:
September 24, 2019
Date of Patent:
April 23, 2024
Assignee:
OSRAM OPTO SEMICONDUCTORS GMBH
Inventors:
Zeljko Pajkic, David Racz, Luca Haiberger
Abstract: In one embodiment, the optoelectronic semiconductor device comprises a semiconductor layer sequence and an electrical via. The semiconductor layer sequence includes an active zone for generating radiation and a contact layer for electrical contacting. The active zone lies in a plane perpendicular to a main growth direction of the semiconductor layer sequence and is located between a first semiconductor region and a second semiconductor region. The contact layer is located within the second semiconductor region. The via extends through the contact layer and preferably ends within the second semiconductor region. A contact surface between the via and the contact layer encloses a contact angle of at least 20° and at most 60° with respect to the plane.
Abstract: In an embodiment a radiation emitting semiconductor chip includes a semiconductor layer sequence with a plurality of active regions and a main extension plane, wherein each active region has a main extension direction, wherein each active region is configured to emit electromagnetic radiation from an emitter region extending parallel to the main extension plane, wherein at least two active regions overlap in plan view, wherein the emitter regions are arranged at grid points of a regular grid connected by at least one grid line, and wherein the main extension direction of at least one active region encloses an angle of at least 10° and at most 80° with the grid lines of the regular grid.
Abstract: The invention relates to a radiation-emitting semiconductor chip comprising a semiconductor layer sequence having at least two active regions which generate electromagnetic radiation during operation and at least one reflective outer surface which is arranged to the side of each active region wherein the reflective outer surface includes an angle of at least 35° and at most 55° with a main extension plane of the semiconductor chip. The invention also relates to a method for producing a radiation-emitting semiconductor chip.
Abstract: A phosphor having the general formula EA7A2T1t1T2t2 T3t3NnOo:RE. EA is selected from the group of divalent elements. A is selected from the group of monovalent elements. T1 is selected from the group of trivalent elements. T2 is selected from the group of tetravalent elements. T3 is selected from the group of pentavalent elements. RE is an activator element. 16+3 t1+4 t2+5 t3?3n?2 o=0. t1+t2+t3=5; n+o=16; 0?t1?4; 0?t2?5; 0?t3?5; 0?n?9; 7?o?16.
Abstract: An optoelectronic semiconductor chip may include a first region doped with a first dopant, a second region doped with a second dopant, an active region between the first and second regions, a first contact layer having an electrically conductive material and covering the first region. An insulating layer may cover the first contact layer and include first openings, and the insulating layer may include a second contact layer having an electrically conductive material and covering the insulating layer and the first openings. The first openings may completely penetrate the insulating layer, and the second contact layer may include second openings and/or a third contact layer comprising an electrically conductive material is arranged in the first openings in each case between the second contact layer and the insulating layer.
Type:
Grant
Filed:
May 15, 2020
Date of Patent:
March 19, 2024
Assignee:
OSRAM Opto Semiconductors GmbH
Inventors:
Fabian Kopp, Attila Molnar, Roland Heinrich Enzmann
Abstract: In an embodiment a vital sign sensor includes an emitter component configured to emit light, a detector component configured to detect light, a first layer of a substantially transparent material, wherein the emitter component is embedded in the first layer, and a second layer of a light scattering material arranged on the first layer, wherein the second layer includes converter particles, and wherein the first layer and the second layer are surrounded by at least one wall of a reflective material.
Type:
Grant
Filed:
March 24, 2020
Date of Patent:
March 19, 2024
Assignee:
OSRAM Opto Semiconductors GmbH
Inventors:
Sergey Kudaev, Reiner Windisch, Dennis Sprenger, Ralph Wirth, Thomas Klafta
Abstract: An arrangement is disclosed. The arrangement comprises at least one semiconductor structure configured to convert a primary radiation into a secondary radiation; an encapsulation layer covering the at least one semiconductor structure; and at least one reflective layer arranged on the encapsulation layer. The semiconductor structure is arranged in a center of the arrangement, and a lateral extent of the arrangement is chosen such that an optically resonant condition is fulfilled for a wavelength of the secondary radiation in the encapsulation layer. Methods for producing an arrangement and an optoelectronic device are also disclosed.
Abstract: A radiation emitting semiconductor chip may include a radiation emitting surface, an epitaxial semiconductor layer sequence having active regions, and a mounting surface facing the radiation emitting surface. The mounting surface may include a plurality of first and second solderable contact surfaces. Each active region may be suppliable with current with a respective first and second solderable contact surface. The first solderable contact surfaces may be arranged in an inner region of the mounting surface. The second solderable contact surface may be arranged in an edge region of the mounting surface. Furthermore, a radiation emitting semiconductor device and a head lamp having such a semiconductor chip may also be useful.
Abstract: A carrier comprises: a main body made of a material comprising a thermal conductivity of at least 380 W/(m K), wherein the main body comprises a mounting surface for mechanical and thermal connection with a component, wherein the main body comprises a recess which penetrates the main body along a first direction perpendicular to the main extension plane of the main body, an electrically insulating filler is arranged in the recess, which comprises a further recess penetrating the filler along the first direction, an inner wall of the filler surrounding the further recess is provided with an electrically conductive coating to form a via through the main body.
Abstract: A luminophore having the general empirical formula X?1?xA?y(Al1+zA?3?z)O4:E? that crystallizes in a tetragonal crystal system. X? may be Mg, Ca, Sr, Ba, and combinations thereof; A? may be Li, Na, K, Rb, Cs, and combinations thereof; E? may be Eu, Ce, Yb, Mn, and combinations thereof; 0<x<0.25; y?x; and z=0.5(2x?y).
Type:
Grant
Filed:
June 4, 2020
Date of Patent:
March 5, 2024
Assignee:
OSRAM Opto Semiconductors GmbH
Inventors:
Daniel Bichler, Simon Dallmeir, Christian Koch, Simon Peschke, Gudrun Plundrich, Philipp Schmid, Christiane Stoll, Johanna Strube-Knyrim, Jutta Thoma, Mark Vorsthove
Abstract: In an embodiment a method includes providing a carrier with an optoelectronic semiconductor chip-component arranged on a top side of the carrier, arranging a first potting material on the top side of the carrier, arranging a second potting material on the first potting material, wherein the second potting material comprises a higher density than the first potting material, wherein a top side of the optoelectronic semiconductor chip-component is covered by neither the first potting material nor the second potting material and allowing a force to act on the first potting material and the second potting material such that the second potting material migrates in a direction toward the top side of the carrier.
Abstract: The invention relates to a method for producing a semiconductor component comprising performing a plasma treatment of an exposed surface of a semiconductor material with halogens, and carrying out a diffusion method with dopants on the exposed surface.
Type:
Grant
Filed:
October 2, 2019
Date of Patent:
February 27, 2024
Assignee:
OSRAM OPTO SEMICONDUCTORS GMBH
Inventors:
Andreas Biebersdorf, Stefan Illek, Christoph Klemp, Ines Pietzonka, Petrus Sundgren
Abstract: In at least one embodiment, the optoelectronic semiconductor chip comprises a semiconductor layer sequence with a radiation side, a first semiconductor layer of a first conductivity type, an active layer, a second semiconductor layer of a second conductivity type, and a rear side, which are arranged one above the other in this order. The active layer generates or absorbs primary electromagnetic radiation in the intended operation. Further, the optoelectronic semiconductor chip comprises a first contact structure and a second contact structure for electrically contacting the semiconductor layer sequence. The second contact structure is arranged on the rear side and is in electrical contact with the second semiconductor layer. The radiation side is configured for coupling in or coupling out primary radiation into or out of the semiconductor layer sequence. The rear side is structured and includes scattering structures configured to scatter and redirect the primary radiation.
Abstract: A circuit for generating a PWM signal includes a shift register having a plurality of clock-controlled register units. Each clock-controlled register unit has an input and an output. The circuit also includes a write unit configured to set the outputs of the register units each to a designated logical value. The circuit further includes a clock generator configured to drive the register units with a common clock signal. The register units are connected in series. The shift register is configured to output the PWM signal at an output contact. The PWM signal is a chronological sequence of the logical values set in the register units, the PWM signal assumes each of the logical values with the duration of one clock of the clock signal, the clock signal is cyclic, during one cycle the duration of successive clocks changes, and the clock signal is identical per cycle.
Type:
Grant
Filed:
April 27, 2020
Date of Patent:
February 20, 2024
Assignee:
OSRAM OPTO SEMICONDUCTORS GMBH
Inventors:
Christopher Soell, Markus Koesler, Jens Richter
Abstract: A semiconductor photodiode (600) comprises a top side (602) with an active surface area (604) for light entry, a bottom side (606), a bulk structure (610) made of a single semiconductor material, the bulk structure comprising a p-type layer (612a) and an n-type layer (612b), which together form the p-n junction (612) of the photodiode, wherein one of the two layers of the p-n junction is an upper p-n junction layer (612a) and the other one is a lower p-n junction layer (612b), wherein the upper p-n junction layer (612a) is located proximate to the active surface area (604), and a semiconductor light absorption layer (614), wherein the light absorption layer (612a), (614) defines the active surface area (604) and is arranged on top of the bulk structure (610), above the upper p-n junction layer (612a), and the semiconductor material of the light absorption layer (614) is different from the semiconductor material of the bulk structure (610), the light absorption layer (614) and the upper p-n junction layer (612
Type:
Grant
Filed:
January 8, 2021
Date of Patent:
January 30, 2024
Assignee:
OSRAM OPTO SEMICONDUCTORS GMBH
Inventors:
Massimo Cataldo Mazzillo, Tim Boescke, Wolfgang Zinkl