Abstract: A computer system including a first computer unit processing user's tasks, a second computer unit performing a halt operation for a virtual memory access, a main memory storing a plurality of virtual accessing data, a buffer memory unit temporarily storing a part of the virtual accessing data and having a faster operation time than that of the main memory, and a control unit controlling the above. The buffer memory unit receives a virtual memory address from the first computer unit and outputs a corresponding actual memory address for accessing the main memory. The control unit includes first and second latches and outputs a bi-state interruption signal and a multilevel interruption signal in response to states of the first and second latch circuits.

Abstract: Disclosed is a display data transfer control apparatus in which a line control memory which can preset raster count data for modifying, in units of lines, an address of a main storage storing a character font to be displayed and character attribute data are provided, and a transfer line in the character font is determined for each line transfer in a DMA transfer sequence, so that, e.g., multi font control, character vertical elongation control, and ruled line vertical extension control, as well as processing character attributes such as an underline and overline, can be realized in the DMA transfer sequence.

Abstract: A display control apparatus using a bit map method, for controlling character attribute data, such as an underline and an overline. In the apparatus, a line control memory is arranged to preset information of character attributes in units of lines of character fonts to be transferred to a video memory; in a DMA transfer sequence of a DMA transfer controller. Character attribute control is performed in a character controller for each line transfer according to the attribute information read out from the line control memory, and expansion of a character font from a character font memory area to the video memory can be simultaneously performed with processing of character attributes from the line control memory.

Abstract: A display control system with a control of background luminance or color data applicable for a personal computer with a paper-white type display device includes a character video signal generation unit, a background luminance setting register, a video enable signal generation unit, a video signal priority unit, and a video signal synthesis unit. A first video enable signal from the video enable signal generation unit controls the supply of the video signals to the video signal priority unit. A second video enable signal from the video enable signal generation unit controls a display of background in a background luminance tone or color designated by the background luminance setting register for an intermediate range when the character video signal is absent.

Abstract: A plurality of processors use a common memory under a time division control mode by way of a time division data bus. In the multiprocessor system, flip-flops are mounted for holding respective write permission flags. Also, a logic gate is employed, operative to allow the processor to write data in the common memory when both the write permission flag and the write request signal from the processor are generated simultaneously. Further, multiplexers are used so that the write operation can be achieved under the time division control mode.

Abstract: A video information transfer processing system in which the contents of a video memory are transferred to a main memory device. This system comprises a color extraction circuit including comparison circuits having logical circuits between the video memory and the main memory device and a DMA controller. Each comparison circuit extracts color information to be transferred in response to designated color factor information and the extracted output is supplied to the main memory device. The DMA controller performs timing control, supply of address information and the like in the above-mentioned processing. By using this system, coloring can be carried out during the transference of the video information and a high speed coloring processing is possible.

Abstract: A condition code producing system for an arithmetic unit which is controlled by a micro program and operate on binary floating point data produces a condition code having a plurality of bits and describing an attribute of the binary floating point data. The condition code producing system comprises: a storing device for storing each bit of the condition code; a device for producing a plurality of detection signals from values of predetermined bits of the binary floating point data. This data is transferred to a bus within the arithmetic unit by a micro instruction which involves a data transfer, where the micro instruction is one of a plurality of micro instructions constituting the micro program. The micro instruction comprises a condition control field constituted by a plurality of bits having values depending on at least precision and data portions of the binary floating point data which is transferred.

Abstract: A computer system capable of interruption using a special protection code for a write interruption region of a main memory, including a subsidiary memory connected with a central processor unit and the main memory. The subsidiary memory delivers a translated real address code and protection codes including ordinary protection codes and the special protection code. Checking of the special protection code in the special protection code check number is carried out when the special protection code from the subsidiary memory is present and an access instruction from the central processor unit is a write instruction. Thereby, writing into a region beyond a stack region in the main memory is possible and the information of execution of the write interruption to the region beyond the stack region in the main memory is transmitted to the central processor unit.

Abstract: A floppy disk unit has a motor drive mechanism and a data read/write circuit, a control means which changes the speed of rotation of motor and the electrical characteristics of the read/write circuit in accordance with the characteristic of the disk used and thereby the disks to be used with different speeds of rotation can be used in the same floppy disk unit.

Abstract: In a data processor for handling data comprising words of n-bits, a plurality of (n+m)-bit registers is provided for use as general purpose and address expansion registers, and effective addresss of (n+m)-bits are generated by adding addresses having n bits and provided in the instructions with the (n+m)-bit content of registers designated by the instructions. Thus, a data processor can be designed so as to have an expandable address bit length and flexible addressing with little additional hardware.

Abstract: A data-transfer controlling system comprising a bus-control unit connected to a common bus for controlling data transfer through the bus and a plurality of transmitter/receiver units for transferring data through the common bus to each other. The bus is comprised of a transfer-request signal line connected to each of the transmitter/receiver units, one or two permission-signal lines, for permitting transfer of data by a transmitter/receiver unit which has been generating a transfer-request signal, an acknowledge signal line, and a transfer-end signal line. The bus does not include a busy-interlock signal line, which was included in the prior art. The transmitter/receiver unit which has received the permission signal begins to transfer data when both of the permission signal and the transfer-end signal are terminated.

Abstract: A lookahead (guessahead) prefetching technique is used to reduce the average access time, for accessing memory modules when program addresses are modified into effective addresses for addressing the modules. A first memory address register stores the column address and module designation portions of the current effective address, a second memory address register stores the row address portion of the current effective address, and a third memory address register stores the module designation portion of the prior effective address. Since the same module is frequently accessed many times in succession, the average access time is reduced by starting an access based upon the contents of the second and third memory address registers without waiting until the column address and module designation portions of the current effective address are available for storage in the first memory address register.

Abstract: A data processing system includes three resources, i.e., a memory, a general purpose register file having a plurality of elements and a stack having a top. The system further includes a first mechanism for making the top of the stack correspond to at least one of the elements in the general purpose register and a second mechanism for controlling the operation of the stack. When the element to which the top of the stack corresponds is specified in an instruction register of the system, the top of the stack is selected to be accessed by the first mechanism and the operation of the stack is controlled by the second mechanism.

Abstract: A direct memory access control (DMAC) system, in a data processing system, includes at least a central processing unit and a memory, the memory being capable of storing and providing data in any one of several predetermined formats. A plurality of input/output control ports, each connecting a respective input/output device to a common data bus, control data transfer in either direction between the device and the memory. A direct memory access control unit is connected to the common data bus for receiving an access request signal from any of the plurality of input/output control ports, and is connected to the memory for providing thereto, in response to the access request signal, instructions at least as to the size and desired format of the data transfer. A bus switching unit connects the common data bus to the memory, and is connected to the direct memory access control unit for receiving the instructions.

Abstract: Disclosed herein is a data communication system which carries out the transfer of data information. In said system, when one communication control unit is used as a transmitting side, said unit sends control signals, such as a receive command signal, to another communication control unit, and; when said one unit is used as a receiving side, said one unit sends control signals, such as various response signals, to said other communication control unit. In the data communication system according to the present invention, the same control signal has different meanings, depending on whether the communication control unit is used as a transmitting side or as a receiving side.

Abstract: In a multiprocessor system having a plurality of processors, each of identical construction, each processor is internally equipped with a fixed address supply source which generates a non-unique fixed address for accessing a common memory unit over commonly connected bus lines, and a sequential state indicate signal generator for generating a logic "1" or "0" synchronizing signal when a special condition (for example, interrupt) occurs with respect to the processor.A shared memory access control system for a multiprocessor system, as above described, includes circuitry, external to and associated with at least each processor except for one processor, responsive to the synchronizing signal from its respective processor for modifying the non-unique fixed address from the respective processor so that, as a result, each processor is able to address the common memory over the commonly connected bus lines with a unique fixed address.