Abstract: A data transferring system having a plurality of devices using a common bus, wherein the devices send out a requesting signal to a requesting signal line for requesting a transfer of data, and in the devices a priority order is assigned to the transference of the data. The system further provides a common control unit for the plurality of devices so as to control the common bus by receiving the requesting signal on the requesting signal line and then sending an acknowledging signal for the transfer of data. Each of the plurality of devices receives the acknowledging signal so that the device which sends out the requesting signal carries out the transfer of data. At least one of the plurality of devices, except for the device having the highest priority order, has a detecting circuit for detecting the requesting signal on the requesting signal line.

Abstract: Described is a data processing system with an improved data processing operation which is comprised of a central processing unit, a main memory unit, a plurality of input/output control units and a common bus which interconnects all of the above units, wherein the common bus includes at least a data channel, an address channel and a tag channel. The tag channel consists of at least a "write service in" line and a "read service in" line, wherein the "write service in" line transfers a signal which indicates, when the write operation is being conducted, whether or not the information on the data channel and the address channel are available, while the "read service in" line transfers a signal which indicates, when the read operation is being conducted, whether or not the information on the address channel is available, whereby a write operation and a read operation are alternately specified in the system without errors. Further, a single means for providing a bus busy signal is mounted in the system.

Abstract: An address extending control circuit is disclosed which is provided with a memory having a memory capacity larger than that assignable with the content of an address register. The memory area of the memory is divided into a common block and a plurality of segment blocks of variable capacity. In a certain processing, the common block and any one of the segment blocks are utilized in pairs, thereby to obtain an extended address. To this end, an address extending address register capable of selecting a predetermined segment block of the memory is provided in addition to the address register. When the value in the address register is detected to be larger than a predetermined value, the content of the address extending address register corresponding thereto is appended to the content of the address register to increase the number of bits and a combination of the common block with one segment block of the memory is selected, with which an address in the selected segment block is accessed.

Abstract: Disclosed is a bidirectional repeater in a data transmission system in which a supervisor is connected to one end of a bidirectional bus having connected thereto a plurality of communication units and the bidirectional bus is extended through the bidirectional repeater. In the case of data transmission between the communication units or between one of the communication units and the supervisor, the bidirectional repeater relays signals without delay and without any erroneous operation even in the case of impulsive noise getting mixed in the signals and determines the data transmitting direction prior to data transmission.