Abstract: A system comprises a tool arrangement; a line including an optical fibre for distributed optical sensing measurements, and an electrically conductive member covered by an electrically insulating material, the line having the outer profile of a slickline; and a termination-coupler which mechanically connects the line to the tool arrangement, electrically connects the electrically conductive member of the line to the tool arrangement, and optically terminates the optical fibre of the line. A method comprises using the optical fibre to perform distributed optical sensing measurements; identifying one or more regions of interest of the elongated space based at least in part on results of the distributed optical sensing measurements; hauling in and/or paying out the line to cause the tool arrangement to move to each region of interest; and electrically transmitting information along the electrically conductive member to cause the tool arrangement to measure the one or more values.

Abstract: A method for performing operations in a well comprises sensing a condition at, adjacent, or within a wellhead arrangement located at an opening of the well and performing a safety procedure in response to the sensed condition to improve the safety of the well operations. The method may comprise sensing the condition when a tool is located at, adjacent to, or within the wellhead arrangement. The sensed condition may be associated with a status of the tool. The sensed condition may be associated with an emission, field or signal transmitted to and/or from the tool, extending to and/or from the tool, and/or coupled to and/or from the tool. Performing the safety procedure may comprise controlling a position or status of the tool or controlling an environment at, adjacent to, or within the wellhead arrangement.

Abstract: A wireline apparatus comprises a sheave for accommodating a wireline and a sheave mounting configured for coupling to a wireline stuffing box. The apparatus includes a sensor for measuring at least one of wireline tension and deployed wireline length at the sheave.

Abstract: A motorcycle including a frame having a backbone and engine carrier prevents the need for front support bars. The power plant is secured to the backbone and engine carrier and may be quickly removed. The power plant turns a hydraulic pump that transfers power to a hydraulic motor via hydraulic fluid. A reservoir of hydraulic fluid is preferably contained in the backbone. The hydraulic motor is contained in a swing arm and connects to one side of the rear wheel. The hydraulic motor acts as both a drive unit and a braking unit. Lights may be secured to the engine carrier to provide a better view of the road.

Abstract: Presented is a trailer incorporating a device that allows the detachable coupling of the ball coupler and safety chains of a trailer for remote storage of these items, while incorporating a security feature that allows only the original ball coupler and safety chains to be connected. This deters the unauthorized towing or theft of the trailer.

Abstract: The MHD sterilization system invention is a method involving the use of magnetohydrodynamics, (MHD) for the specific purpose of destroying populations of micro-organisms occurring in, within or on fluid, semi-fluid, semi-solid or solid materials.

Abstract: A CMOS integrated circuit structure with planarized self-aligned transistors and local planarization in the vicinity of the transistors so as to allow an interconnect, with a planar upper surface, which is free of bridging, has good continuity over the planarized topography and is compatible with self-alignment schemes, hence conserving chip real estate. The structure is compatible with planarization using BPSG, BPTEOS, SOG or CMP. After formation of self-aligned insulated transistor gates and active transistor regions, a "landing pad" is formed on the substrate at the buried contact and polyiso contact locations so as to allow more effective etching at the exact location of the buried contact and polyiso contact. Then the integrated circuit structure is locally planarized by formation of an oxide layer and a reflowed overlying glass layer. The glass layer is etched back to planarize the surface.

Abstract: An MOS transistor for use in an integrated circuit is fabricated with a self-aligning contact and interconnect structure which allows for higher packing density. Self-aligning source and drain contacts overlap the gate but are prevented from a short circuiting to the gate by oxide insulation between the source/drain contacts and the gate, and a layer of silicon nitride above the gate. Contacts to the gate are made on top of the gate over the active region of the transistor because the source and drain regions are protected by a hardened layer of photoresist during etching of insulation to expose the gate contact. Source, drain and gate contacts are protected by a layer of titanium silicide so that interconnects are not required to completely cover these areas. Low resistance interconnects are formed of doped polysilicon covered by titanium silicide encapsulated by a thin film of titanium nitride.

Abstract: An MOS transistor for use in an integrated circuit, particularly CMOS integrated circuits, is fabricated with a self-aligning contact and interconnect structure which allows for higher packing density. Self-aligning source and drain contacts overlap the gate but are prevented from short circuiting to the gate by oxide insulation between the source/drain contacts and the gate, and a layer of silicon nitride above the gate. Contacts to the gate are made on top of the gate over the active region of the transistor because the source and drain regions are protected by a hardened layer of photoresist during etching of insulation to expose the gate contact. Source, drain and gate contacts are protected by a layer of titanium silicide so that interconnects are not required to completely cover these areas. Low resistance interconnects are formed of titanium silicide encapulated by a thin film of titanium nitride.

Abstract: The invention provides fast generation of flag signals for devices such as a first-in first-out buffers by looking ahead and predetermining flag signals for future possible states of the device. Predetermining flag signals does not delay flag output because the required calculations are completed before the flag signal is needed. The flag signal can be changed when needed as quickly as a multiplexer can switch from an old flag signal to a predetermined flag signal. The switching time of a multiplexer is shorter than the comparator delays in prior art flag generators.

Abstract: A synchronous SRAM (or DRAM or other logic) chip with input registers (or latches) associated with the chip memory cell array input lines, where there is logic associated with the registers, locates the logic gates upstream of the registers and connected to the D input of each register. Hence the logic gates not only provide the needed logic function, but also provide the necessary delay to meet the specified hold time delay in synchronous circuits. This reduces the logic function after the input registers and hence improves the clock-to-output access time of the chip.

Abstract: An MOS transistor for use in an integrated circuit is fabricated with a self-aligning contact and interconnect structure which allows for higher packing density. Self-aligning source and drain contacts overlap the gate but are prevented from a short circuiting to the gate by oxide insulation between the source/drain contacts and the gate, and a layer of silicon nitride above the gate. Contacts to the gate are made on top of the gate over the active region of the transistor because the source and drain regions are protected by a hardened layer of photoresist during etching of insulation to expose the gate contact. Source, drain and gate contacts are protected by a layer of titanium silicide so that interconnects are not required to completely cover these areas. Low resistance interconnects are formed of doped polysilicon covered by titanium silicide encapsulated by a thin film of titanium nitride.

Abstract: A CMOS integrated circuit uses self-aligned transistors combined with local planarization in the vicinity of the transistors so as allow local interconnects which are free of bridging, have good continuity over the planarized topography and are compatible with the self-alignment schemes, hence conserving chip real estate. After formation of self-aligned insulated transistor gates and active transistor regions, the integrated circuit structure is planarized by formation of an oxide layer and a reflowed overlying glass layer. The glass layer and underlying oxide layer are removed only in the area of the buried contact, while an overlying metal or polysilicon conductive layer contacts the upper surface of certain of the transistor gate structures, the topside insulating layer of which has been removed for this purpose.

Abstract: The invention provides fast generation of flag signals for devices such as a first-in first-out buffers by looking ahead and predetermining flag signals for future possible states of the device. Predetermining flag signals does not delay flag output because the required calculations are completed before the flag signal is needed. The flag signal can be changed when needed as quickly as a multiplexer can switch from an old flag signal to a predetermined flag signal. The switching time of a multiplexer is shorter than the comparator delays in prior art flag generators.

Abstract: An oxynitride passivation layer and/or fuse protective layer for an SRAM cell having load resistors, where the composition of the oxynitride layer minimizes the effect of hydrogen diffusion on the resistance of underlying load resistors. The index of refraction of the oxynitride is between 1.60 and 1.85. This oxynitride does not substantially diffuse hydrogen into the load resistors even when heated to temperatures over 400.degree. C., and hence, avoids altering resistance during subsequent annealing steps.

Abstract: A compact static random access memory is formed using both split word lines and self aligned contacts. Self aligned contacts between gates of the pull-down transistor and cross-couple interconnects decreases the critical spacing between elements of the cell and permit the cell to be smaller or more manufacturable. The use of split word lines allows memory cell connections to the bit lines to be located on opposite sides of a memory cell. The connections are widely separated along a direction parallel to the bit lines so perpendicular separation between the bit lines can be decreased. The split word lines also allow the memory cell lay out to be symmetric and thereby increases stability. Use of self aligned contacts further decreases the necessary separation between the bit lines. A further feature is a straight conductor which runs though the center of the memory cell and connects the source of the pull-down transistors to a reference voltage V.sub.SS.

Abstract: An in-hole oil-drilling probe is mountable in a drill string to measure hydrocarbon concentrations in drilling fluid flowing around the drill string. The probe consists of a drill collar which is mountable in the drill string. A solvent, in which hydrocarbons are soluble, circulates within the drill collar through a hydrocarbon detection chamber. A membrane in the drill collar has an outer surface positioned to contact flowing drilling fluid and an inner surface positioned to contact circulating solvent within the drill collar. The membrane allows hydrocarbons to permeate from the drilling fluid into the solvent and into the hydrocarbon detection chamber with the solvent. A radiant energy source directs radiant ultra-violet energy into the hydrocarbon detection chamber. A sensor apparatus measures fluorescent energy radiating from the hydrocarbon detection chamber to determine solvent hydrocarbon concentration.

Abstract: Transistor fabrication methods are provided which are suitable, for example, for transistors with current carrying elements above a semiconductor substrate. Only few mask alignments define critical dimensions such as the channel length of a MOS transistor. In one embodiment in which the channel region overlies the gate, a first mask is formed over the channel region, and then an LDD implant is carried out. A second mask is then formed over the LDD portion of the drain region. The second mask is allowed to extend over the first mask. A heavy doping implant is then carried out. Thus an LDD structure can be provided on the drain side but not on the source side with only one mask--the first mask--defining the channel length. In some embodiments, both masks include photoresist. The first photoresist mask is hardened to prevent its lifting during development of the resist of the second mask.

Abstract: A CMOS integrated circuit fabrication technique for forming self-aligned transistors combined with local planarization in the vicinity of the transistors so as to allow local interconnects which are free of bridging, have good continuity over the planarized topography and are compatible with the self-alignment schemes, hence conserving chip real estate. The technique is compatible with planarization schemes using BPSG, BPTEOS, SOG or CMP. After formation of self-aligned insulated transistor gates and active transistor regions, the integrated circuit structure is planarized by formation of an oxide layer and a reflowed overlying glass layer. The glass layer is etched back to planarize the surface. Using a buried contact mask the remaining portions of the glass layer and underlying oxide layer are removed in the area of the buried contact only.

Abstract: A load resistor for use in a semiconductor integrated circuit consists of two portions of conductive material, typically strips of either a silicide or a composite polycrystalline silicon layer and silicide layer formed thereon, formed on a semiconductor substrate and separated from each other by a selected distance. An electrically conductive dopant diffusion barrier is formed on the first and second portions of conductive material. A polycrystalline silicon material is then placed on the structure such that one portion of the polycrystalline silicon material is in ohmic contact through the diffusion barrier with the first portion of conductive material and the other portion of the polycrystalline silicon material is in ohmic contact through the diffusion barrier with the second portion of conductive material. Typically the polycrystalline silicon material is placed on an insulation layer formed on the semiconductor substrate in the portion of the substrate between the two portions of conductive material.