Abstract: A load resistor for use in a semiconductor integrated circuit consists of two portions of conductive material, typically strips of either a silicide or a composite polycrystalline silicon layer and silicide layer formed thereon, formed on a semiconductor substrate and separated from each other by a selected distance. An electrically conductive dopant diffusion barrier is formed on the first and second portions of conductive material. A polycrystalline silicon material is then placed on the structure such that one portion of the polycrystalline silicon material is in ohmic contact through the diffusion barrier with the first portion of conductive material and the other portion of the polycrystalline silicon material is in ohmic contact through the diffusion barrier with the second portion of conductive material. Typically the polycrystalline silicon material is placed on an insulation layer formed on the semiconductor substrate in the portion of the substrate between the two portions of conductive material.
Type:
Grant
Filed:
July 1, 1991
Date of Patent:
December 1, 1992
Assignee:
Paradigm Technology, Inc.
Inventors:
Norman Godinho, Frank T. Lee, Hsiang-Wen Chen, Richard F. Motta, Juine-Kai Tsang, Joseph Tzou, Jai-man Baik, Ting-Pwu Yen
Abstract: An MOS transistor for use in an integrated circuit, particularly CMOS integrated circuits, is fabricated with a self-aligning contact and interconnect structure which allows for higher packing density. Self-aligning source and drain contacts overlap the gate but are prevented from short circuiting to the gate by oxide insulation between source/drain contacts and the gate, and a layer of silicon nitride above the gate. Contacts to the gate are made on top of the gate over the active region of the transistor because the source and drain regions are protected by a hardened layer of photoresist during etching of insulation to expose the gate contact. Source, drain and gate contacts are protected by a layer of titanium silicide so that interconnects are not required to completely cover these areas. Low resistance interconnects are formed of titanium silicide encapsulated by a thin film of titanium nitride.
Type:
Grant
Filed:
January 12, 1990
Date of Patent:
November 24, 1992
Assignee:
Paradigm Technology, Inc.
Inventors:
Norman Godinho, Frank T. Lee, Hsiang-Wen Chen, Richard F. Motta, Juine-Kai Tsang, Joseph Tzou, Jai-man Baik, Ting-Pwu Yen
Abstract: A compact cell design for a static random access memory cell is achieved. The cell has two transistors with gates substantially parallel to each other. One interconnect connects the gate of one transistor to an electrode of the other transistor. Another interconnect connects the gate of the other transistor to an electrode of the first transistor. The two gates and the two interconnects form substantially a rectangle. A power supply circiut line is disposed outside the rectangle. This line and the two interconnects are formed from one conductive layer.
Type:
Grant
Filed:
July 19, 1990
Date of Patent:
June 23, 1992
Assignee:
Paradigm Technology, Inc.
Inventors:
Norman Godinho, Tsu-Wei F. Lee, Hsiang-Wen Chen, Richard F. Motta, Juine-Kai Tsang, Joseph Tzou, Jai-Man Baik, Ting-Pwu Yen
Abstract: Heavily soiled shop towels, mops and other industrial laundry are initially contacted with a mixture of a cleaning solvent and an emulsifier to efficiently penetrate the industrial soil in the fabric. Thereafter water is added to provide an oil-in-water emulsion cleaning composition which effectively removes both the industrial soil and the solvent from the goods. A preferred class of hydrocarbon solvents suitable for this purpose is the class of solvents known as terpene solvents. Particularly suitable are terpene solvents having a tagg closed cup flash point, of 140.degree. F. or higher. The oil-in-water emulsion thereafter is demulsified for separation of the cleaning solvent from the water and recycle of the solvent to the process.