Patents Assigned to PDF Solutions, Inc.
  • Publication number: 20210142122
    Abstract: Classifying wafers using Collaborative Learning. An initial wafer classification is determined by a rule-based model. A predicted wafer classification is determined by a machine learning model. Multiple users can manually review the classifications to confirm or modify, or to add user classifications. All of the classifications are input to the machine learning model to continuously update its scheme for detection and classification.
    Type: Application
    Filed: October 14, 2020
    Publication date: May 13, 2021
    Applicant: PDF Solutions, Inc.
    Inventors: Tomonori Honda, Richard Burch, John Kibarian, Lin Lee Cheong, Qing Zhu, Vaishnavi Reddipalli, Kenneth Harris, Said Akar, Jeffrey D David, Michael Keleher, Brian Stein, Dennis Ciplickas
  • Publication number: 20210118754
    Abstract: A machine learning model for each die for imputing process control parameters at the die. The model is based on wafer sort parametric measurements at multiple test sites across the entire wafer, as well as yield results for the wafer. This allows for a better analysis of outlier spatial patterns leading to improved yield results.
    Type: Application
    Filed: October 16, 2020
    Publication date: April 22, 2021
    Applicant: PDF Solutions, Inc.
    Inventors: Richard Burch, Qing Zhu, Jonathan Holt
  • Publication number: 20210117861
    Abstract: A sequence of models accumulates r-squared values for an increasing number of variables in order to quantify the importance of each variable to the prediction of a targeted yield or parametric response.
    Type: Application
    Filed: October 16, 2020
    Publication date: April 22, 2021
    Applicant: PDF Solutions, Inc.
    Inventors: Richard Burch, Qing Zhu, Jonathan Holt, Tomonori Honda
  • Patent number: 10978438
    Abstract: An IC that includes a contiguous standard cell area with a 4×3 e-beam pad that is compatible with advanced manufacturing processes and an associated e-beam testable structure.
    Type: Grant
    Filed: June 29, 2019
    Date of Patent: April 13, 2021
    Assignee: PDF Solutions, Inc.
    Inventors: Stephen Lam, Dennis Ciplickas, Tomasz Brozek, Jeremy Cheng, Simone Comensoli, Indranil De, Kelvin Doong, Hans Eisenmann, Timothy Fiscus, Jonathan Haigh, Christopher Hess, John Kibarian, Sherry Lee, Marci Liao, Sheng-Che Lin, Hideki Matsuhashi, Kimon Michaels, Conor O'Sullivan, Markus Rauscher, Vyacheslav Rovner, Andrzej Strojwas, Marcin Strojwas, Carl Taylor, Rakesh Vallishayee, Larg Weiland, Nobuharu Yokoyama, Matthew Moe
  • Publication number: 20210103489
    Abstract: Scheme for detection and classification of semiconductor equipment faults. Sensor traces are monitored and processed to separate known abnormal operating conditions from unknown abnormal operating conditions. Feature engineering permits focus on relevant traces for a targeted feature. A machine learning model is built to detect and classify based on an initial classification set of anomalies. The machine learning model is continuously updated as more traces are processed and learned.
    Type: Application
    Filed: October 6, 2020
    Publication date: April 8, 2021
    Applicant: PDF Solutions, Inc.
    Inventors: Richard Burch, Jeffrey D. David, Qing Zhu, Tomonori Honda, Lin Lee Cheong
  • Patent number: 10897814
    Abstract: A characterization vehicle may include a first test circuit and a second test circuit located on separate panels of a panelized printed circuit (PC) board. The first test circuit may be fabricated in accordance with a first plurality of design parameters. The second test circuit may be fabricated in accordance with a second plurality of design parameters. The first plurality of design parameters and the second plurality of design parameters may be chosen in accordance with a design of experiment (DOE) concerning one or more design rules or design trade-offs such that at least two corresponding design parameters from the first and second test circuits have identical values, and at least two corresponding design parameters from the first and second test circuits have different values.
    Type: Grant
    Filed: December 17, 2019
    Date of Patent: January 19, 2021
    Assignee: PDF Solutions, Inc.
    Inventor: Brian E. Stine
  • Publication number: 20200388545
    Abstract: A maintenance tool for semiconductor process equipment and components. Sensor data is evaluated by machine learning tools to determine when to schedule maintenance action.
    Type: Application
    Filed: August 25, 2020
    Publication date: December 10, 2020
    Applicant: PDF Solutions, Inc.
    Inventors: Tomonori Honda, Jeffrey Drue David, Lin Lee Cheong
  • Patent number: 10854522
    Abstract: A method for processing a semiconductor wafer uses non-contact electrical measurements indicative of at least one tip-to-side short or leakage, at least one corner short or leakage, and at least one via open or resistance, where such measurements are obtained from non-contact pads associated with respective tip-to-side short, corner short, and via open test areas.
    Type: Grant
    Filed: March 31, 2018
    Date of Patent: December 1, 2020
    Assignee: PDF Solutions, Inc.
    Inventors: Stephen Lam, Dennis Ciplickas, Tomasz Brozek, Jeremy Cheng, Simone Comensoli, Indranil De, Kelvin Doong, Hans Eisenmann, Timothy Fiscus, Jonathan Haigh, Christopher Hess, John Kibarian, Sherry Lee, Marci Liao, Sheng-Che Lin, Hideki Matsuhashi, Kimon Michaels, Conor O'Sullivan, Markus Rauscher, Vyacheslav Rovner, Andrzej Strojwas, Marcin Strojwas, Carl Taylor, Rakesh Vallishayee, Larg Weiland, Nobuharu Yokoyama
  • Patent number: 10852337
    Abstract: Described are test structures and methods for measuring silicon thickness in fully depleted silicon-on-insulator technologies.
    Type: Grant
    Filed: June 1, 2017
    Date of Patent: December 1, 2020
    Assignee: PDF Solutions, Inc.
    Inventors: Sharad Saxena, Tomasz Brozek, Yuan Yu, Mike Kyu Hyon Pak, Meindert Martin Lunenborg
  • Patent number: 10803221
    Abstract: Described is a method for implementing a snap to capability that enables the manufactured of a valid pattern in a semiconductor device, based upon an originally invalid pattern.
    Type: Grant
    Filed: September 5, 2017
    Date of Patent: October 13, 2020
    Assignee: PDF Solutions, Inc.
    Inventors: Elizabeth Lagnese, Jonathan Haigh
  • Patent number: 10777470
    Abstract: Testing data is evaluated by machine learning tools to determine whether to include or exclude chips from further testing.
    Type: Grant
    Filed: March 26, 2019
    Date of Patent: September 15, 2020
    Assignee: PDF Solutions, Inc.
    Inventors: Lin Lee Cheong, Tomonori Honda, Rohan D. Kekatpure, Lakshmikar Kuravi, Jeffrey Drue David
  • Patent number: 10777472
    Abstract: An IC includes a contiguous standard cell area with first, second, and third TS-GATE-short-configured test area geometries disposed therein. In some embodiments, the contiguous standard cell area may further include: fourth and fifth TS-GATE-short-configured test area geometries, and/or other test area geometries, such as tip-to-tip-short, tip-to-side-short, diagonal-short, corner-short, interlayer-overlap-short, via-chamfer-short, merged-via-short, snake-open, stitch-open, via-open, or metal-island-open.
    Type: Grant
    Filed: September 29, 2018
    Date of Patent: September 15, 2020
    Assignee: PDF Solutions, Inc.
    Inventors: Stephen Lam, Dennis Ciplickas, Tomasz Brozek, Jeremy Cheng, Simone Comensoli, Indranil De, Kelvin Doong, Hans Eisenmann, Timothy Fiscus, Jonathan Haigh, Christopher Hess, John Kibarian, Sherry Lee, Marci Liao, Sheng-Che Lin, Hideki Matsuhashi, Kimon Michaels, Conor O'Sullivan, Markus Rauscher, Vyacheslav Rovner, Andrzej Strojwas, Marcin Strojwas, Carl Taylor, Rakesh Vallishayee, Larg Weiland, Nobuharu Yokoyama
  • Patent number: 10768222
    Abstract: Described here is an apparatus and method of testing a vertical (3D) semiconductor memory structure coupled between word lines and bit lines, by means of a direct connections of a plurality of test pads to word lines and bit lines of the memory structure on memory product wafer. Such connections are created by modified patterns of metal lines through contacts and vias created on the memory product wafer. The described apparatus and method are used for detecting electrical continuity (opens and shorts) in the memory structure, calculating resistance of selected word lines or bit cell strings, or performing more complex tests of memory bit cell transistors. The result of this detection can then be used to find defective regions or memory cells in the semiconductor memory structure. Such a testing device may be referred to as a direct testing system.
    Type: Grant
    Filed: June 4, 2018
    Date of Patent: September 8, 2020
    Assignee: PDF SOLUTIONS, INC.
    Inventor: Tomasz Brozek
  • Patent number: 10734293
    Abstract: Techniques for measuring and/or compensating for process variations in a semiconductor manufacturing processes. Machine learning algorithms are used on extensive sets of input data, including upstream data, to organize and pre-process the input data, and to correlate the input data to specific features of interest. The correlations can then be used to make process adjustments. The techniques may be applied to any feature or step of the semiconductor manufacturing process, such as overlay, critical dimension, and yield prediction.
    Type: Grant
    Filed: November 25, 2015
    Date of Patent: August 4, 2020
    Assignee: PDF SOLUTIONS, INC.
    Inventor: Jeffrey Drue David
  • Patent number: 10679723
    Abstract: Disclosed is a system and method for performing direct memory characterization of memory cells in a memory array using peripheral transistors. A memory array is fabricated using a mask layer defining routing for a set of first stage periphery transistors electrically connected to the word lines of the memory array. A revised mask is used for defining a different routing for a set of second stage periphery transistors including different characteristics than the first stage periphery transistors. Testing is conducted by applying a simulated Erase signal to the nonvolatile memory cells and determining which cells are erased. Based on this test, certain characteristics of the first and/or second stage periphery transistors can be identified that provide improved conditions for the nonvolatile memory cells. A product chip can be manufactured using modified versions of the first stage periphery transistors that incorporate the characteristics that provide the improved condition(s).
    Type: Grant
    Filed: December 6, 2018
    Date of Patent: June 9, 2020
    Assignee: PDF SOLUTIONS, INC.
    Inventors: Dong Kyu Lee, Kelvin Yih-Yuh Doong, Tuan Pham, Klaus Schuegraf, Christoph Dolainsky, Huan Tsung Huang, Hendrik Schneider
  • Patent number: 10656204
    Abstract: Disclosed is a system and method for collecting trace data of integrated circuits from the back-end assembly tools and using yield, reliability, and burn-in data to distinguish good circuit traces from bad ones. Described further is an system and method for implementing a heuristic mapping of trace data for distinguishing between good or bad traces in an Internet-based or offline application. The result of this detection can then be used for yield improvement or for burn-in reduction where for example burn-in chips having “good” circuit traces are subjected to thermal stress for less time than for chips identified as having “bad” circuit traces.
    Type: Grant
    Filed: September 21, 2018
    Date of Patent: May 19, 2020
    Assignee: PDF Solutions, Inc.
    Inventors: Brian Stine, Richard Burch, Nobuchika Akiya
  • Patent number: 10641804
    Abstract: Described is a CBCM technique that works only with PMOS transistors or only with NMOS transistors. Specifically, a method of monitoring performance of an integrated circuit device using a CBCM technique is disclosed, the method comprising: providing a metrology structure having a pseudo-inverter comprising a pull-up pull-down transistor switch, wherein the transistor switch comprises a pull-up transistor and a pull-down transistor of the same type; charging and discharging a device under test (DUT) coupled to the pseudo-inverter using a non-overlapping clock; measuring capacitance of the DUT with a gate voltage of the pull-up transistor at a preset value; and, using the value of the measured capacitance to estimate a dimension of a structure in the integrated circuit device. The non-overlapping clock is generated by: turning the pull-down transistor off when the pull-up transistor is on; and, turning the pull-down transistor on when the pull-up transistor is off.
    Type: Grant
    Filed: September 19, 2016
    Date of Patent: May 5, 2020
    Assignee: PDF Solutions, Inc.
    Inventor: Sharad Saxena
  • Patent number: 10643735
    Abstract: An apparatus and method for testing two-terminal memory elements organized as a cross-point memory array. The apparatus allows functional testing of two-terminal memory elements organized as a cross-point memory array, and built in a short flow manufacturing process. The proposed apparatus substantially eliminates the use of any type of additional active or passive switches, selectors, or decoders. A large number of memory elements of various memory types including planar (two dimensional) or three dimensional memory structures can be tested without the need of manufacturing selectors or running the full flow process.
    Type: Grant
    Filed: July 11, 2018
    Date of Patent: May 5, 2020
    Assignee: PDF Solutions, Inc.
    Inventors: Tomasz Brozek, Christopher Hess, Rakesh Vallishayee, Meindert Lunenborg, Hendrik Schneider, Yuan Yu, Amit Joag, SiewHoon Ng
  • Patent number: 10622344
    Abstract: The present invention relates to IC chips containing a mixture of standard cells obtained from an original set of design rules and enhanced standard cells that are a variant of the original set of design rules and methods for making the same.
    Type: Grant
    Filed: July 7, 2017
    Date of Patent: April 14, 2020
    Assignee: PDF SOLUTIONS, INC.
    Inventors: Jonathan Haigh, Elizabeth Lagnese
  • Patent number: 10593604
    Abstract: Improved processes for manufacturing wafers, chips, or dies utilize in-line data obtained from non-contact electrical measurements (“NCEM”) of fill cells that contain structures configured target/expose a variety of open-circuit, short-circuit, leakage, or excessive resistance failure modes. Such processes may involve evaluating Designs of Experiments (“DOEs”), comprised of multiple NCEM-enabled fill cells, in at least two variants, all targeted to the same failure mode(s).
    Type: Grant
    Filed: April 4, 2016
    Date of Patent: March 17, 2020
    Assignee: PDF Solutions, Inc.
    Inventors: Stephen Lam, Dennis Ciplickas, Tomasz Brozek, Jeremy Cheng, Simone Comensoli, Indranil De, Kelvin Doong, Hans Eisenmann, Timothy Fiscus, Jonathan Haigh, Christopher Hess, John Kibarian, Sherry Lee, Marci Liao, Sheng-Che Lin, Hideki Matsuhashi, Kimon Michaels, Conor O'Sullivan, Markus Rauscher, Vyacheslav Rovner, Andrzej Strojwas, Marcin Strojwas, Carl Taylor, Rakesh Vallishayee, Larg Weiland, Nobuharu Yokoyama