Abstract: A semiconductor image classifier. Convolution functions are applied to modify the wafer images in order to extract key information about the image. The modified images are condensed then processed through a series of pairwise classifiers, each classifier configured to determine that the image is more like one of the pair than the other. Probabilities from each classifier are collected to form a prediction for each image.

Abstract: A robust predictive model. A plurality of different predictive models for a target feature are run, and a comparative analysis provided for each predictive model that meet minimum performance criteria for the target feature. One of the predictive models is selected, either manually or automatically, based on predefined criteria. For semi-automatic selection, a static or dynamic survey is generated for obtaining user preferences for parameters associated with the target feature. The survey results will be used to generate a model that illustrates parameter trade-offs, which will be used to finalize the optimal predictive model for the user.

Abstract: Semiconductor yield is modeled at the die level to predict die that are susceptible to early lifetime failure (ELF). A first die yield calculation is made from parametric data obtained from wafer testing in a semiconductor manufacturing process. A second die yield calculation is made from die location only. The difference between the first die yield calculation and the second die yield calculation is a prediction delta. Based on an evaluation of the first die yield calculation and the prediction delta, the likelihood of early lifetime failure can be identified and an acceptable level of die loss can be established to remove die from further processing.

Abstract: An IC that includes a contiguous standard cell area with a 4x3 e-beam pad that is compatible with advanced manufacturing processes and an associated e-beam testable structure.

Abstract: An IC that includes a contiguous standard cell area with a 4×3 e-beam pad that is compatible with advanced manufacturing processes and an associated e-beam testable structure.

Abstract: An IC that includes a contiguous standard cell area with a 4×3 e-beam pad that is compatible with advanced manufacturing processes and an associated e-beam testable structure.

Abstract: An IC that includes a contiguous standard cell area with a 4×3 e-beam pad that is compatible with advanced manufacturing processes and an associated e-beam testable structure.

Abstract: A model is generated for predicting failures at the wafer production level. Input data from sensors is stored as an initial dataset, then data exhibiting excursions or useless impact is removed from the dataset. The dataset is converted into target features, where the target features are useful in predicting whether a wafer will be normal or not. A trade-off between positive and negative results is selected, and a plurality of predictive models are created. The final model is selected based on the trade-off criteria, and deployed.

Abstract: Robust machine learning predictions. Temporal dependencies of process targets for different machine learning models can be captured and evaluated for the impact on process performance for target. The most robust of these different models is selected for deployment based on minimizing variance for the desired performance characteristic.

Abstract: A method for predicting yield for a semiconductor process. A particular type of wafer is fabricated to have a first set of features disposed on the wafer, with a wafer map identifying a location for each of the first set of features on the wafer. Data from wafer acceptance tests and circuit probe tests is collected over time for wafers of that particular type as made in a semiconductor fabrication process, and at least one training dataset and a least one validation dataset are created from the collected data. A second set of “engineered” features are created and also incorporated onto the wafer and wafer map. Important features from the first and second sets of features are identified and selected, and using those important features as inputs, a number of different process models are run, with yield as the target. The results of the different models can be combined, for example, statistically.

Abstract: An IC that includes a contiguous standard cell area with a 4×3 e-beam pad that is compatible with advanced manufacturing processes and an associated e-beam testable structure.

Abstract: Classifying wafers using Collaborative Learning. An initial wafer classification is determined by a rule-based model. A predicted wafer classification is determined by a machine learning model. Multiple users can manually review the classifications to confirm or modify, or to add user classifications. All of the classifications are input to the machine learning model to continuously update its scheme for detection and classification.

Abstract: A machine learning model for each die for imputing process control parameters at the die. The model is based on wafer sort parametric measurements at multiple test sites across the entire wafer, as well as yield results for the wafer. This allows for a better analysis of outlier spatial patterns leading to improved yield results.

Abstract: A sequence of models accumulates r-squared values for an increasing number of variables in order to quantify the importance of each variable to the prediction of a targeted yield or parametric response.

Abstract: An IC that includes a contiguous standard cell area with a 4×3 e-beam pad that is compatible with advanced manufacturing processes and an associated e-beam testable structure.

Abstract: Scheme for detection and classification of semiconductor equipment faults. Sensor traces are monitored and processed to separate known abnormal operating conditions from unknown abnormal operating conditions. Feature engineering permits focus on relevant traces for a targeted feature. A machine learning model is built to detect and classify based on an initial classification set of anomalies. The machine learning model is continuously updated as more traces are processed and learned.

Abstract: A characterization vehicle may include a first test circuit and a second test circuit located on separate panels of a panelized printed circuit (PC) board. The first test circuit may be fabricated in accordance with a first plurality of design parameters. The second test circuit may be fabricated in accordance with a second plurality of design parameters. The first plurality of design parameters and the second plurality of design parameters may be chosen in accordance with a design of experiment (DOE) concerning one or more design rules or design trade-offs such that at least two corresponding design parameters from the first and second test circuits have identical values, and at least two corresponding design parameters from the first and second test circuits have different values.

Abstract: A maintenance tool for semiconductor process equipment and components. Sensor data is evaluated by machine learning tools to determine when to schedule maintenance action.

Abstract: A method for processing a semiconductor wafer uses non-contact electrical measurements indicative of at least one tip-to-side short or leakage, at least one corner short or leakage, and at least one via open or resistance, where such measurements are obtained from non-contact pads associated with respective tip-to-side short, corner short, and via open test areas.

Abstract: Described are test structures and methods for measuring silicon thickness in fully depleted silicon-on-insulator technologies.