Abstract: Improved processes for manufacturing wafers, chips, or dies utilize in-line data obtained from non-contact electrical measurements (“NCEM”) of fill cells that contain structures configured target/expose a variety of open-circuit, short-circuit, leakage, or excessive resistance failure modes. Such processes may involve evaluating Designs of Experiments (“DOEs”), comprised of multiple NCEM-enabled fill cells, in at least two variants, all targeted to the same failure mode(s).

Abstract: Disclosed techniques conform standard cells in an integrated circuit design into a valid template pattern using a template-based approach to standard cell design. The template architecture stores valid patterns of circuit elements for the design. A Boolean expression comprising an aggregated set of Boolean assertions can be generated for each different combination of cell shape features and edge locations with the cell design to compute a solution that matches with a valid pattern in one of the templates. If the solution evaluates to a Boolean TRUE result, the cell shape(s) can be modified in accordance with the solution. If not, the granularity can be updated by incrementing an “adjustment neighborhood” value and iterating the computations for shape features and edge locations using the updated values for the analysis until a Boolean TRUE result is found or it is determined there is no solution for the set of expressions.

Abstract: Improved methods for manufacturing semiconductor product wafer with the additional use of non-product masks are described. According to certain aspects of the invention, an evaluation wafer is first manufactured by utilizing at least one non-product mask to process one or more layer(s) on the evaluation wafer, and subsequently utilizing at least one unaltered product mask to process an evaluation-region-of-interest on the evaluation wafer. The evaluation-region-of-interest is evaluated by measuring the state of one or more feature(s) in the evaluation-region-of-interest using voltage contrast inspection (VCi). The measurements are then used to identify failures in the evaluation-region-of-terest. In response to identifying a failure in the evaluation-region-of-interest, the manufacturing process is improved by modifying at least one parameter associated with at least one processing step and manufacturing product wafers utilizing the at least one processing step(s) with the at least one modified parameter(s).

Abstract: Methods of measuring fin height electrically for devices fabricated using FinFET technology are disclosed here. One method uses an interleaving comb-like test structure with no gate. The other method extracts fin height from total gate capacitance from FinFETS with varying gate lengths. When a comb-like structure with no gate is used to measure fin height, if there is another structure with a gate is used, then the gate capacitance may be measured to independently measure thickness of gate dielectric.

Abstract: A characterization vehicle may include a first test circuit and a second test circuit located on separate panels of a panelized printed circuit (PC) board. The first test circuit may be fabricated in accordance with a first plurality of design parameters. The second test circuit may be fabricated in accordance with a second plurality of design parameters. The first plurality of design parameters and the second plurality of design parameters may be chosen in accordance with a design of experiment (DOE) concerning one or more design rules or design trade-offs such that at least two corresponding design parameters from the first and second test circuits have identical values, and at least two corresponding design parameters from the first and second test circuits have different values.

Abstract: A memory-specific implementation of a test and characterization vehicle utilizes a design layout that is a modified version of the product mask. Specific routing is used to modify the product mask in order to facilitate memory cell characterization. This approach can be applied to any memory architecture with word-line and bit-line perpendicular or substantially perpendicular to each other, including but not limited to, volatile memories such as Static Random Access Memory (SRAM), Dynamic RAM (DRAM), non-volatile memory such as NAND Flash (including three-dimensional NAND Flash), NOR Flash, Phase-change RAM (PRAM), Ferroelectric RAM (FeRAM), Correlated electron RAM (CeRAM), Magnetic RAM (MRAM), Resistive RAM (RRAM), XPoint memory and the like.

Abstract: A method is disclosed for designing a test vehicle utilizing a layout of a real integrated circuit (IC) product. The method comprises: importing an original full-chip layout of the real IC product; partitioning the original full-chip layout into probe groups, each probe group comprising probe pads, and, a plurality of IC devices within an area of interest (AOI) having original routing interconnect for those IC devices; selecting a set of IC devices within the AOI; and, for the selected set of IC devices, using pattern extraction to remove the original routing interconnect, and create customized interconnect layers (CIL) to reconfigure connection between the individual IC devices. Incorporating the selected set of IC devices with the CIL into the original full-chip layout creates a modified full-chip layout such that a wafer fabricated using the modified full-chip layout comprises a real product with a built-in test vehicle.

Abstract: A method for processing a semiconductor wafer uses non-contact electrical measurements indicative of at least one tip-to-tip short or leakage, at least one via-chamfer short or leakage, and at least one corner short or leakage, where such measurements are obtained from cells with respective tip-to-tip short, via-chamfer short, and corner short test areas, using a charged particle-beam inspector with a moving stage and beam deflection to account for motion of the stage.

Abstract: Described is a method of reducing multitudes of input data signals to a manageable plurality of input data signals and using the manageable plurality of input data signals to obtain response data that is provided to the semiconductor wafer, packaging, or design facility.

Abstract: An IC includes first and second designs of experiments (DOES), each comprised of at least two fill cells. The fill cells contain structures configured to obtain in-line data via non-contact electrical measurements (“NCEM”). The first DOE contains fill cells configured to enable non-contact (NC) detection of tip-to-side shorts, and the second DOE contains fill cells configured to enable NC detection of corner shorts.

Abstract: An improved standard cell chip, library and/or process ensures that there is adequate spacing between TSCUT jogs and nearby gate contacts to avoid inadvertent shorts/leakages that can degrade manufacturing yield or performance.

Abstract: A method for processing a semiconductor wafer uses non-contact electrical measurements indicative of at least one tip-to-tip short or leakage, at least one tip-to-side short or leakage, and at least one corner short or leakage, where such measurements are obtained from non-contact pads associated with respective tip-to-tip short, tip-to-side short, and corner short test areas.

Abstract: A method for processing a semiconductor wafer uses non-contact electrical measurements indicative of at least one tip-to-tip short or leakage, at least one tip-to-side short or leakage, and at least one side-to-side short or leakage, where such measurements are obtained from non-contact pads associated with respective tip-to-tip short, tip-to-side short, and side-to-side short test areas.

Abstract: A method for processing a semiconductor wafer uses non-contact electrical measurements indicative of at least one tip-to-side short or leakage, at least one chamfer short or leakage, and at least one corner short or leakage, where such measurements are obtained from non-contact pads associated with respective tip-to-side short, chamfer short, and corner short test areas.

Abstract: A method for processing a semiconductor wafer uses non-contact electrical measurements indicative of a resistance through a stitch, where such measurements are obtained by scanning a pad comprised of at least three electrically connected, parallel conductive stripes using a moving stage with beam deflection to account for motion of the stage.

Abstract: A method for processing a semiconductor wafer uses non-contact electrical measurements indicative of at least one tip-to-tip short or leakage, at least one side-to-side short or leakage, and at least one via open or resistance, where such measurements are obtained from non-contact pads associated with respective tip-to-tip short, side-to-side short, and via open test areas.

Abstract: A method for processing a semiconductor wafer uses non-contact electrical measurements indicative of at least one side-to-side short or leakage, at least one via-chamfer short or leakage, and at least one corner short or leakage, where such measurements are obtained from cells with respective side-to-side short, via-chamfer short, and corner short test areas, using a charged particle-beam inspector with a moving stage and beam deflection to account for motion of the stage.

Abstract: A method for processing a semiconductor wafer uses non-contact electrical measurements indicative of at least one tip-to-side short or leakage, at least one chamfer short or leakage, and at least one via open or resistance, where such measurements are obtained from non-contact pads associated with respective tip-to-side short, chamfer short, and via open test areas.

Abstract: A method for processing a semiconductor wafer uses non-contact electrical measurements indicative of at least one tip-to-tip short or leakage, at least one tip-to-side short or leakage, and at least one side-to-side short or leakage, where such measurements are obtained from cells with respective tip-to-tip short, tip-to-side short, and side-to-side short test areas, using a charged particle-beam inspector with a moving stage and beam deflection to account for motion of the stage.

Abstract: A method for processing a semiconductor wafer uses non-contact electrical measurements indicative of at least one side-to-side short or leakage, at least one corner short or leakage, and at least one via open or resistance, where such measurements are obtained from non-contact pads associated with respective side-to-side short, corner short, and via open test areas.