Abstract: A method and system for the design and implementation of an optimally factored filter is presented. Pairs of angle values are organized in pairing candidates and a threshold is defined to indicate an upper bound on the number of pairing candidates. A first pairing candidate is exchanged above the threshold with a second pairing candidate below the threshold and a matrix is generated based on the pairing candidates below the threshold. A lowest predicted total quantization cost between all pairing candidates represented within the matrix is determined and the pairing candidates that result in the lowest predicted total quantization cost are used to determine the coefficients of the filter.

Abstract: A method and system for the design and implementation of an optimally factored interpolated finite impulse response (IFIR) filter is presented. Techniques used to increase the implementation efficiency of the filter include joint sequencing of the filter stages, use of an nested IFIR filter, taming of a stage by relocation of that stage, fusing two or more stages together to form a single stage, and manual manipulation of a post-stage multiplier. IFIR filters using this approach may be realized as low pass filters or high pass filters, and in either analog or digital form.

Abstract: An apparatus and method for angle rotation is disclosed to rotate a complex input by the angle ? to produce a rotated complex output signal. A memory storage device generates control information based on a coarse angle ?M. A coarse rotation butterfly circuit uses the control information to rotate the complex input signal by the coarse angle ?M to produce an intermediate complex number. The control information controls one or more multiplexers and/or adders in the coarse rotation butterfly circuit to rotate the complex input signal. The fine rotation butterfly circuit uses the control information to rotate the intermediate complex number by a fine angle ?L to produce the complex output signal. The control information controls one or more multiplexers and/or adders in the fine rotation butterfly circuit to rotate the intermediate complex number.

Abstract: Systems and methods for a split phase accumulator having a plurality of sub phase accumulators are provided, Each sub phase accumulator receives a portion of a frequency control word. The first sub phase accumulator includes a first register and the remaining sub phase accumulators include a register and an overflow register. At each discrete point in time, the first sub phase accumulator is configured to be responsive to the first portion of the frequency control word at that discrete point in time and to the first sub phase accumulator value at the immediately previous discrete point in time, and each of the remaining sub phase accumulators is configured to be responsive to a value of its corresponding portion of the frequency control word at that discrete point in time and to the same second sub phase accumulator value at the immediately previous discrete point in time.

Abstract: An apparatus and method for angle rotation is disclosed to rotate a complex input by the angle ? to produce a rotated complex output signal. A memory storage device generates control information based on a coarse angle ?M. A coarse rotation butterfly circuit uses the control information to rotate the complex input signal by the coarse angle ?M to produce an intermediate complex number. The control information controls one or more multiplexers and/or adders in the coarse rotation butterfly circuit to rotate the complex input signal. The fine rotation butterfly circuit uses the control information to rotate the intermediate complex number by a fine angle ?L to produce the complex output signal. The control information controls one or more multiplexers and/or adders in the fine rotation butterfly circuit to rotate the intermediate complex number.

Abstract: A method and system for the design and implementation of an inverse-sinc function that can efficiently process signals produced by high-speed systems is presented. An integrated inverse-sinc module accepts multiple data streams that may result from parallel sub-systems and creates multiple outputs that can be interleaved to produce a sequence that has been filtered by an inverse-sinc function. The multiple-input, multiple-output system may be beneficially operated at a low data rate, such as the data rate used by each of the sub-systems.

Abstract: A method and system for the design and implementation of filters is presented in which the filter's transfer function can be provided with a significant insensitivity to the filter's tap coefficient values. A desensitized digital filter includes a first halfband filter and a second filter coupled in cascade between an input of the digital filter and the output of the digital filter. In embodiments, the first filter has the transfer function F(z)=K(1+z?1)(1+z?1) wherein K?0 is a scale factor. The digital filter may also interact with an up-sampler or a down-sampler. A desensitized Hilbert transformer includes an FIR filter having filter-tap coefficients whose absolute values equal the absolute values of the coefficients of an FIR filter F(z) for which the product (1+z?1)F(z) is a halfband filter coupled in cascade with a second filter.

Abstract: A method and system for the design and implementation of desensitized digital filters with droop correction. The desensitized digital filter includes a first filter configured to receive an input signal, a decimator or upsampler, and a modified desensitized half-band filter. The first filter introduces droop into the passband of the desensitized digital filter. The desensitized half-band filter has a transfer function F(z)=K(1+z?1)G(z) wherein K?0 is a scale factor, that is modified to omit a (1+z?1) factor block. The modified desensitized half-band filter compensates for the passband droop introduced by the first filter. The first filter may be a sinc filter, CIC filter, or filter having similar properties.

Abstract: An apparatus and method for angle is disclosed to rotate a complex input by the angle ? to produce a rotated complex output signal. A memory storage device generates control information based on a coarse angle ?M. A coarse rotation butterfly circuit uses the control information to rotate the complex input signal by the coarse angle ?M to produce an intermediate complex number. The control information controls one or more multiplexers and/or adders in the coarse rotation butterfly circuit to information to rotate the complex input signal. The fine rotation butterfly circuit uses the control information to rotate the intermediate complex number by a fine angle ?L to produce the complex output signal. The control information controls one or more multiplexers and/or adders in the fine rotation butterfly circuit to rotate the intermediate complex number.

Abstract: A tail-tank coupling technique combines two complementary differential LC-VCOs to form a quadrature LC-VCO. The technique reduces phase noise by providing additional energy storage for noise redistribution and by cancelling noise injected by transistors when they operate in the triode region. The resulting noise factor is close to the theoretical minimum 1+?, similar to a differential LC-VCO driven by an ideal noiseless current source. However, its figure-of-merit is higher, due to the absence of voltage head-room being consumed by a current source. The optimal ratio of tail-tank capacitor to main-tank capacitor for minimizing phase noise is approximately 0.5. The method can be extended to combine any even number of LC tanks resonating at fo and 2fo to form an integrated oscillator producing quadrature phase at frequency fosc and differential output at 2fosc.

Abstract: A method and system for the design and implementation of filters is presented in which the filter's transfer function can be provided with a significant insensitivity to the filter's tap coefficient values. A desensitized digital filter includes a first halfband filter and a second filter coupled in cascade between an input of the digital filter and the output of the digital filter. In embodiments, the first filter has the transfer function F(z)=K(1+z?1)(1+z?1) wherein K?0 is a scale factor. The digital filter may also interact with an up-sampler or a down-sampler. A desensitized Hilbert transformer includes an FIR filter having filter-tap coefficients whose absolute values equal the absolute values of the coefficients of an FIR filter F(z) for which the product (1+z?1)F(z) is a halfband filter coupled in cascade with a second filter.

Abstract: An improved DDFS includes a minority-bit detector to permit a series of cascaded transformation stages to perform half or less than half of the rotational operations otherwise required by detecting whether the required rotation or non-rotation operations are in the minority and performing only the operations in the minority. This substantially reduces the number of minority-select butterfly stages that would otherwise be required. The cascaded transformation stages include a preliminary set of lookup tables in ROM memory, one of which is selected in accordance with the minority-bit detector and may include a subsequent set of butterfly stages providing the inputs to the minority-select butterfly stages.

Abstract: The present invention is embodied in a system for the analysis and design of direct digital synthesizers including a windowing engine, and a method that enables the analysis of DDS output spectra in the presence of phase truncation and arbitrary approximations and errors in the implementation of the sine/cosine mapping function (SCMF) without the need to approximate the DDS characteristics.

Abstract: A method and system for the design and implementation of an inverse-sinc function that can efficiently process signals produced by high-speed systems is presented. An integrated inverse-sinc module accepts multiple data streams that may result from parallel sub-systems and creates multiple outputs that can be interleaved to produce a sequence that has been filtered by an inverse-sinc function. The multiple-input, multiple-output system may be beneficially operated at a low data rate, such as the data rate used by each of the sub-systems.

Abstract: An adder for adding a signal at a first input (A) and a second input (B) to produce an adder output (S) is disclosed. The adder comprises a bypass input (bypass) and a logic circuit, communicatively coupled to the bypass input (bypass), the first input (A), and the second input (B), the logic circuit configured to hold at least one of the first input (A) and the second input (B) according to the bypass input (bypass).

Abstract: An angle rotator uses a coarse stage rotation and a fine stage rotation to rotate an input complex signal in the complex plane according to an angle ?. The coarse stage rotation includes a memory device storing pre-computed cosine ?M and sine ?M values for fast retrieval, where ?M is a radian angle that corresponds to a most significant word (MSW) of the input angle ?. The fine stage rotation uses one or more error values that compensate for approximations and quantization errors associated with the coarse stage rotation. The rotator consolidates operations into a small number of reduced-size multipliers, enabling efficient multiplier implementations such as Booth encoding, yielding a smaller and faster overall circuit.

Abstract: A method of synchronizing symbol timing in a digital device includes the steps of receiving complex data samples of one or more symbols, correlating the data samples with a complex conjugate of a preamble data set, selecting between real and imaginary samples and generating a complex number based on the result. The method then determines an angle in a complex plane that represents symbol synchronization for the digital device. Disclosed embodiments include applications to communications devices, and to carrier recovery in such devices. In such embodiments the resultant angle may represent a carrier phase offset for the device.

Abstract: A rectangular-to-polar-converter receives a complex input signal (having X0 and Y0 components) and determines an angle ? that represents the position of the complex signal in the complex plane. The rectangular-to polar-converter determines a coarse angle ?1 and a fine angle ?2, where ?=?1+?2. The coarse angle ?1 is obtained using a small arctangent table and a reciprocal table. These tables provide just enough precision such that the remaining fine angle ?2 is small enough to approximately equal its tangent value. Therefore the fine angle ?2 can be obtained without a look-up table, and the fine angle computations are consolidated into a few small multipliers, given a precision requirement. Applications of the rectangular-to-polar converter include symbol and carrier synchronization, including symbol synchronization for bursty transmissions of packet data systems. Other applications include any application requiring the rectangular-to-polar conversion of a complex input signal.

Abstract: A trigonometric interpolator interpolates between two data samples at an offset &mgr;, where the two data samples are part of a set of N data samples. The trigonometric interpolator fits a trigonometric polynomial to the N data samples and evaluates the trigonometric polynomial at the offset &mgr;. The trigonometric inteprolator can be utilized for data rate changing and to correct mismatches between received samples and transmitted symbols. Simulations demonstrate that the trigonometric interpolater attains better performance than “conventional” interpolators, while simultaneously reducing the required hardware. In embodiments, the filter response of the trigonometric interpolator can be modified to achieve an arbitrary frequency response in order to enhance the interpolator performance. More specifically, the frequency response of the interpolator can be shaped to effectively correspond with the frequency response of the input data samples and the offset &mgr;.

Abstract: A method, apparatus, article of manufacture, and a memory structure for low power digital processing is disclosed. Tap values are modified by one or more factors to increase computational efficiency and a bias factor used to compensate for changes in the processor output response that result from the modification of the tap values.