Abstract: A method, apparatus, article of manufacture, and a memory structure for low power digital processing is disclosed. Tap values are modified by one or more factors to increase computational efficiency and a bias factor used to compensate for changes in the processor output response that result from the modification of the tap values.

Abstract: A method, apparatus, article of manufacture, and a memory structure for low power digital filtering. The method comprises the steps of successively delaying each of the input values {x0,x1, . . . ,xN−1} to create tap values {t0,t1, . . . ,tN−1}, multiplying each of the tap values {t0,t1, . . . ,tN−1} by A•{h0,h1, . . . ,hN−1} to produce {At0h0,At1h1, . . . ,AtN−1hN−1}wherein values {h0,h1, . . . ,hN−1} are weight values selected to achieve a desired filter response and A is a factor selected to improve computational efficiency in filtering the input data stream, summing the values {At0h0,At1h1, . . .

Abstract: The present invention comprises a direct digital frequency synthesizer. A phase accumulator provides a normalized angle .theta. to a sine/cosine generator that outputs the value of the sine/cosine function at the provided angle. The she/cosine generator in a preferred embodiment comprises a plurality of multiplierless butterfly and carry-save stages in cascade that perform angle rotations on a phasor on the unit circle whose x and y coordinates correspond to cosine and sine values. To calculate the sine and cosine values at a particular angle .theta.=b.sub.1 .theta..sub.1 +b.sub.2 .theta..sub.2 +. . . +b.sub.N .theta..sub.N where b.sub.k .epsilon. {0, 1} are the binary bits and the .theta..sub.k =2.sup.-k are the associated positional weights, each of the butterfly and carry-save stages rotate the phasor by an amount .theta..sub.k =2.sup.-k. The direction of the rotation, clockwise or counter-clockwise, depends upon the value of the binary bits b.sub.k.