Abstract: A VDD-to-VSS clamp shunts current from a power node to a ground node within an integrated circuit chip when an electro-static-discharges (ESD) event occurs. A resistor and capacitor in series between power and ground generates a low voltage on a trigger node between the resistor and capacitor when an ESD event occurs. A p-channel transistor with its gate driven by the trigger node turns on, driving a gate node high. The gate node is the gate of an n-channel shunt transistor that shunts ESD current from power to ground. A p-channel feedback transistor terminates the ESD shunt current. The p-channel feedback transistor is connected between power and the trigger node, in parallel with the resistor, and has the gate node as its gate. When a latch up trigger occurs, such as electron injection, voltage drops across an N-well of the resistor is prevented by the parallel p-channel feed-back transistor.

Abstract: A stable voltage that is independent of supply voltage is applied to a pair of current sources. A first current source generates a first current that passes through a first resistor, setting a compare-input voltage. A source-input voltage is applied to the first current source to vary the first current and the compare-input voltage. A second current source generates a stable current that passes through a second resistor, setting a reference voltage. The compare-input voltage and the reference voltage are applied to inputs of a comparator that generates an output voltage that indicates when the source-input voltage causes the compare-input voltage to rise past the reference voltage. The first and second currents track each other over temperature and process variations and are independent of supply voltage. A more accurate comparison of the source-input voltage is thus made.

Abstract: A bus switch has reduced input capacitance. Parasitic source-to-well and drain-to-well capacitors are shorted by well-shorting transistors, eliminating these parasitic capacitances. The well-shorting transistors are turned on when the bus-switch transistor is turned on, but are turned off when the bus-switch transistor is turned off and the bus switch isolates signals on its source and drain. The isolated P-well under the bus-switch transistor and the well-shorting transistors is not tied to ground. Instead the isolated P-well is floating when the bus-switch transistor is turned on. When the bus-switch transistor is turned off, the underlying isolated P-well is driven to ground by a biasing transistor in another P-well. Since the isolated P-well has a much lower doping than the N+ source and drain, the capacitance of the well-to-substrate junction is much less than the source-to-well capacitance. Thus input capacitance is reduced, allowing higher frequency switching.

Abstract: A stable voltage that is independent of supply voltage is applied to a pair of current sources. A first current source generates a first current that passes through a first resistor, setting a compare-in-put voltage. A source-input voltage is applied to the first current source to vary the first current and the compare-input voltage. A second current source generates a stable current that passes through a second resistor, setting a reference voltage. The compare-input voltage and the reference voltage are applied to inputs of a comparator that generates an output voltage that indicates when the source-input voltage causes the compare-input voltage to rise past the reference voltage. The first and second currents track each other over temperature and process variations and are independent of supply voltage. A more accurate comparison of the source-input voltage is thus made.

Abstract: A self-biasing differential buffer generates a self-bias voltage from its inputs. A first amplifier receives a first input signal on gates of four transistors—p and n-channel drive transistors in a drive branch and p and n-channel bias-generating transistors in a bias-generating branch. Current source and current sink transistors source and sink current to both branches. The drains of the drive transistors drive a differential output, while the drains of the bias-generating transistors drive through a transmission gate to a self-bias node. The second amplifier receives the second input signal and has the same structure, with one branch driving the self-bias voltage through another transmission gate, and another branch driving a complementary differential output. The bias-generating branches use smaller transistors so that only a small current is used to generate the self-bias voltage. The self-bias node is fed to the gates of current source and sink transistors.

Abstract: A module board has trace impedances that are matched at trace junctions. An input line that drives a signal to a junction has its impedance adjusted to match the equivalent impedance of branch traces output from the junction. Since input and output impedances match, reflections caused by the junction are minimized or eliminated. The input impedance can match by being within 20% of the equivalent impedance of the branch lines. The equivalent impedance of branches is the reciprocal of the sum of the individual branch lines' reciprocal impedance. Termination can be eliminated when such junctions are impedance-matched. Secondary junctions can also be impedance-matched, allowing for a variety of trace topologies. Such trace-impedance matching is especially useful for memory modules.

Abstract: A divide by X.5 circuit can be implemented as a divided by 1.5 circuit. A phase-locked loop (PLL) has a quadrature voltage-controlled oscillator (VCO) that generates four phases offset at 0, 90, 180, and 270 degrees. Differential signals from the VCO are converted to single-ended VCO clocks that drive four divide-by-3 circuits, each clocked by one of the four phases of the VCO clocks. Resets to the divide-by-3 circuits are staggered to activate each divide-by-3 circuit synchronously with its phase clock. Outputs from the divide-by-3 circuits are applied to a frequency doubler that generates the final clock that is 1.5 times slower than the VCO clocks. The final clock has a near 50%-50% duty cycle.

Abstract: Transistors with very thin gate oxides are protected against oxide failure by cascading two or more transistors in series between an output pad and ground. The intermediate source/drain node between the two cascaded transistors is usually floating during an ESD test, delaying snapback turn-on of a parasitic lateral NPN transistor. This intermediate node is used to drive the gate of an upper trigger transistor. A lower trigger transistor has a gate node that is charged by the ESD pulse on the pad through a coupling capacitor. When the coupled ESD pulse turns on the trigger transistors, the trigger transistors turn on a silicon-controlled rectifier (SCR) that is integrated with the trigger transistors.

Abstract: A phase-locked loop (PLL) has an analog divider in the feedback path that receives either the in-phase or quadrature-phase pair of outputs from a voltage-controlled oscillator (VCO) while the other pair, 90-degree out-of-phase, of outputs from the VCO is used for the PLL output. Phases between the PLL's input and output are inherently aligned. The analog output of the analog divider is converted to a digital clock signal and applied to a cascade of digital dividers to generate a reduced feedback clock. The reduced feedback clock is applied to the D input and the digital clock signal is applied to the clock input of a pseudo D-flip-flop that drives the feedback input of a phase-frequency detector that drives the charge pump to the VCO input. Another cascade of digital dividers and pseudo D-flip-flop re-align the reference clock input to the phase-frequency detector. Analog and digital re-alignment circuits reduce internal skew.

Abstract: A register chip for double-data-rate (DDR) memory modules operates in 1:1 mode or 1:2 mode. A differential input clock is buffered to generate a slave clock that continuously clocks slave stages of flip-flops, and gated to generate a first clock pulsing only in 1:1 mode and a second clock pulsing only in 1:2 mode. The master stage has two input transmission gates, one activated by the first clock and another activated by the second clock. In 1:1 mode a first data bit is sampled by the first clock, but in 1:2 mode a second data bit is sampled by the second clock. The sampled bit is inverted and applied to the slave stage and to a feedback gate that has transistors gated by the first and second clocks. The clock-to-output delay is improved since an output mux is replaced by the muxing function built into the master stage.

Abstract: A differential input buffer shows reduced sensitivity to input conditions such as input-trace loading and upstream driver characteristics. Varying input conditions can be measured as differences in amplitude, slew rate, and common-mode offset. Wide input-voltage swings are clamped to a limited voltage range by an input clamp circuit that uses source followers to drive p-channel clamp transistors that turn off when the input voltage is too low. A voltage divider then sets the lowest voltage input to a differential stage. The differential stage receives the clamped inputs and has two tail current sinks to reduce delay sensitivity to charging and discharging of tail capacitances. A middle voltage is applied to transistors opposite the differential transistors that receive the clamped input voltages. A bias voltage for the tail current sinks is generated by mirroring currents and setting a gate voltage by injecting and removing a same bias current from a resistor.

Abstract: A voltage-variable capacitor uses the channel-to-substrate junction from a gated diode formed from a metal-oxide-semiconductor transistor. The transistor gate has at least two contacts that are biased to different voltages. The gate acts as a resistor with current flowing from an upper gate contact to a lower gate contact. The gate-to-source voltage varies as a function of the position. A critical voltage is where the gate-to-source voltage is equal to the transistor threshold. A portion of the gate that has gate voltages above the critical voltage has an inversion layer or conducting channel under the gate. Another portion of the gate has gate voltages below the critical voltage, and thus no channel forms. By varying either the gate voltages or the source voltage, the area of the gate that has a channel under it is varied, varying the channel-to-substrate capacitance. Separate gate arms reduce bias current.

Abstract: A power-down mode is activated when equal voltages are detected on a pair of differential inputs. The voltage difference across the differential inputs is applied to a multiplier, which generates a squared difference. The squared difference is smoothed and filtered by a low-pass filter to produce an average signal. The average signal is compared to a reference voltage, either explicitly or implicitly, to detect when the voltage difference across the differential inputs is too small. A power-down signal is activated when the average signal is too small. The multiplier can be implemented with a Gilbert cell, while a filter-comparator converts the differential Gilbert-cell output to a single-ended signal and filters the signal. The reference voltage compared can be set by the switching threshold of the filter comparator or other logic gates. A complementary Gilbert cell and filter-comparator can be used to increase the operating range.

Abstract: Presence or absence of a differential clock is detected. The voltage of each differential clock line is compared to the common-mode voltage and integrated over time by a capacitor. The capacitor is discharged during the portions of the clock cycle that the differential line is over the common-mode voltage. If the clock stops pulsing the capacitor is charged by a current source to activate a clock-loss signal. The clock-loss detector is ideal for high-frequency operation since each differential clock line is applied to only one transistor gate. The common-mode voltage generates a bias voltage for a differential amplifier that receives the true and complement differential clock lines. Diodes prevent capacitor charging by reverse current flow from the differential amplifier when the clock is inactive. The averaged peak voltage or envelope of the differential input signals is detected.

Abstract: A phase-locked loop (PLL) keeps tracking a reference clock when a frequency offset is introduced. The PLL has primary and secondary PLL loops. A digital-to-analog converter (DAC) generates a current that is passed through an offset resistor to generate an offset voltage. An op amp is inserted in the primary loop between a filter capacitor and a voltage-controlled oscillator (VCO). The offset resistor is coupled between the inverting input of the op amp and the op amp's output. When the DAC offset occurs, the voltage to the VCO and the frequency of the primary loop change and the primary loop loses tracking of the reference clock. The secondary loop keeps tracking the reference clock during the DAC offset while the primary loop is open. Then the output clock of the secondary loop is applied as the feedback clock to the phase comparator of the primary loop.

Abstract: ESD protection is provided by local ESD-protection devices between each pad and a common-discharge line (CDL). Each ESD-protection device has p-well or p-substrate taps to a local ground rather than to the CDL, reducing noise coupling from the I/O's through the CDL. Another ESD clamp that bypasses the CDL is provided between each pair of internal power and ground buses. Better protection of core circuits during power-to-ground ESD events is provided by bypassing the CDL since only one ESD clamp rather than two ESD-protection devices must turn on. The ESD clamps and ESD-protection devices can be gate-coupled n-channel transistors with coupling capacitors between the pad and the transistor gate. Devices can also be substrate-triggered transistors or active ESD clamps that include an inverter between a coupling capacitor to the CDL and the n-channel transistor gate.

Abstract: A cross-pin electro-static-discharge (ESD) protection device protects against ESD zaps between two I/O pins. Pin A is connected to a drain of a bus-switch transistor and pin B is connected to the transistor's source. An ESD protection device on pin A has an n-channel shunting transistor to an internal ground bus. The gate of the shunting transistor is a cross-gate node that is capacitivly coupled to pin A, and has a leaker resistor to ground. An n-channel cross-grounding transistor has its gate connected to the same cross-gate node, but it connects the internal ground bus to pin B, which is grounded in the pin-to-pin ESD test. An ESD pulse on pin A drives the cross-gate node high, turning on both the shunting transistor and the cross-grounding transistor. The floating internal ground bus is connected to ground by pin B, grounding the substrate of the bus-switch transistor to prevent its turn-on.

Abstract: A buffer chip clocks data to memories on a memory module. The data-input path to registers or flip-flops on the buffer chip are speeded up by removing muxes on the inputs to the flip-flops. Speeding up the data-input path allows power dissipation to be reduced, since smaller input buffers can be used. Control logic combines chip-select and data-strobe control inputs that prevent clocking of the flip-flops. The control logic outputs a combined strobe signal. Set-reset latches are triggered by the combined strobe signal. The set-reset latches allow the clock to pass through to the flip-flop when the chip-select and data-strobe inputs are both active. The set-reset latches block a rising transition of chip-select and data-strobe inputs from changing the clocks to the flip-flop, thus preventing data-clocking errors.

Abstract: A bus-switch transistor connects two I/O pins when an enable signal on its gate is activated. Each pin has an electro-static-discharge (ESD) protection devices. When the internal ground and the enable are floating, and an ESD pulse is applied between the two pins, an isolation circuit couples part of the ESD pulse to the gate of the bus-switch transistor, keeping the transistor turned off. This forces the ESD pulse to travel through the ESD protection devices, preventing damage to the bus-switch transistor. The isolation circuit has a capacitor between a pin and the gate of a coupling transistor. The capacitor couples the ESD pulse to the gate of the coupling transistor. The coupling transistor turns on, connecting the pin to the gate of a grounding transistor. The grounding transistor then turns on, connecting the gate of the bus-switch transistor to the other pin, which is grounded during the ESD test.

Abstract: A bi-directional bus-interface chip has no direction-control input. A forward buffer and a reverse buffer are both normally disabled in the high-impedance state. When a transition occurs on one input bus, a driver transistor in the forward or reverse buffer is activated to pass the transition through the bus-interface chip. After a delay, the driver transistor is disabled. An optional bus-hold circuit maintains voltage levels on buses when driver transistors are disabled. The delay can be selectable by shorting delay resistors in the delay circuit. The high-level voltages on the two busses may differ. The bus-interface chip converts one voltage domain to another and can re-generate weak signals. A pre-buffer may be added to gradually step up the voltage level when differences in voltage domains are large.