Abstract: A clock generator uses two PLL loops and a variable resistor to generate a variable output frequency from a single fixed-frequency reference clock. Each PLL loop receives the reference clock and phase-compares it with a feedback clock. The feedback clock in one loop is slightly faster in frequency than the feedback clock in the second loop. The input voltages to voltage-controlled oscillators (VCOs) in the two loops thus vary slightly. A variable resistor is connected between the two inputs to the VCOs. The variable resistor has a center tap that can be selected from locations along the variable resistor. The center tap voltage is input to a final VCO that generates the variable output frequency. The output frequency is varied by selecting the center tap's location along the variable resistor. The variable resistor can be constructed from a series of sub-resistors with the center-tap location chosen by select transistors acting as a multiplexer.

Abstract: Ground and power-supply bounce are reduced for a CMOS output buffer. An n-channel driver transistor and a p-channel driver transistor are attached to the output pad. The gate of the n-channel driver transistor is driven by a pre-driver inverter. The pre-driver is a CMOS inverter except that the p-channel source is connected to power through a p-channel and an n-channel source-control transistor in parallel. The n-channel source-control transistor has its gate connected to power so that it remains on. The p-channel source-control transistor has its gate driven by feedback. The feedback is buffered from the output pad, or inverted from the gate of the driver transistor. When the output buffer switches, only the n-channel source-control transistor is initially on, so the current charging the driver gate is limited. The driver turns on slowly at first. Later, the feedback turns on the p-channel source-control transistor, increasing (doubling) the current to charge the driver gate.

Abstract: A differential amplifier has a wide common-mode input range since it uses two complementary amplifiers. One amplifier has a differential pair of n-channel transistors while the other amplifier has a differential pair of p-channel transistors. The input range is extended further by replacing the current mirror transistors with load resistors. The load resistors continue to supply current to the differential pair transistors even when the input is within a transistor-threshold of the power or ground rails. The current through the load resistors is mirrored to intermediate mirror transistors that have their gate connected to the resistor's terminal node. Current in the differential amplifiers is mirrored as if current-mirror transistors were present rather than the load transistors. The intermediate mirror transistors supply current to inverse-mirror transistors.

Abstract: An isolating output buffer is operated by a low-voltage Vcc power supply, yet can be put in a high-impedance state. The output buffer does not draw significant current when its output is driven by an external driver to a voltage above Vcc. The over-voltage on the output pad is coupled to the n-well under p-channel transistors through a fixed-gate p-channel transistor. The over-voltage from the n-well is then coupled to a source node through another p-channel transistor. The source node is the source of a p-channel transistor that drives the gate of a p-channel driver transistor driving the output pad. The source node is normally driven to Vcc by another p-channel transistor. The p-channel transistor can be split into two driver transistors that are separately driven by two isolating inverters or gates. The isolating gates have p-channel transistors connected to the source node. Using split drivers can reduce noise and di/dt when the two driver transistor are enabled at slightly different times.

Abstract: An output buffer for a line driver uses transmission gates for active termination. A large p-channel driver is pulsed on during a low-to-high output transition, but this driver is turned off once the output voltage reaches a threshold. A feedback circuit includes a sensing inverter that has its input connected to the output node. The sensing inverter causes the gate of the p-channel driver to be driven high once the output swings past the threshold. A similar n-channel driver transistor is pulsed on during a low-going output transition but is disabled by a feedback circuit that senses the output voltage falling below a threshold. A pullup transmission gate is also connected between the output and the power supply, while a pulldown transmission gate is connected between the output and ground. Each transmission gate contains a p-channel and a n-channel transistor in parallel.

Abstract: A fully duplex cordless telephone has a transmitter and a receiver connected to a common antenna. A broad-band antenna coupler such as a ferrite-core hybrid transformer may replace a more costly duplexer with filters. Since all characteristics of the transmit signal are known, the transmit signal removes itself from the receiver by signal cancellation. The canceling signal is extracted from the composite signal from within the receiver front end, after the antenna coupler and low noise amplifier. This composite signal is coupled to the first input of a difference amplifier, and the output of this amplifier is coupled to the remainder of the receiver. The composite signal is coupled to the second input, after its smaller receive component has been further suppressed, and its remaining transmit signal has been adjusted by two feedback control systems to restore its phase and amplitude to be equal to the transmit component of the composite signal.

Abstract: A gate-array cell uses smaller and larger transistors. Four larger transistors are provided: two n-channel and two p-channel. A small p-channel transistor is placed between the contact tabs of the polysilicon lines of the two larger p-channel transistors, and between the p-channel transistors and a N-well tap. A small n-channel transistor is similarly placed between the contact tabs of polysilicon lines of the two larger n-channel transistors, and between the n-channel transistors and a P-well tap. The cell is slightly expanded in height to accommodate the two smaller transistors. The smaller transistors enable a reduction in the number of transistors required for latches and flip-flops. The smaller transistors allow a feedback inverter to directly connect to an input, since the input can easily over-power the feedback current. This is not possible for standard gate array cells having only one transistor size. Transmission gates are eliminated when direct feedback is feasible.

Abstract: A more accurate charge pump reduces phase error in a PLL. An UP input pulse causes a p-channel drive transistor to charge a filter capacitor on the output, while a down DN input pulse causes an n-channel drive transistor to discharge the output. The drive transistors are connected to power or ground through a supply transistor. The supply transistor is biased on in the linear region and is not switched off. The sources of the drive transistors are always driven by the supply transistors, preventing phase error from floating sources. The drive transistors are common-gate switches with their gates biased by a compensating bias generator. The p-channel drive transistor current variations with Vds are compensated by providing a similar current variation to the n-channel drive transistor. Thus the bias is adjusted to compensate for drain-source voltage changes that can cause the up and down currents from the drive transistors to mismatch.

Abstract: An electro-static-discharge (ESD) protection circuit protects internal power supplies in a mixed-signal IC. An active protection circuit is used. The ESD-protection circuit uses standard transistors and is actively enabled and disabled by standard transistors. A standard thin-oxide NMOS transistor is the ESD switch (shunt) between power supply busses. This thin-oxide transistor ESD switch is actively enabled and disabled by a control circuit. NMOS transistors in the control circuit discharge the gate node of the ESD switch when the power supplies are powered up, thus actively disabling the ESD protection circuit. When an ESD pulse is applied to a supply when powered down, a capacitor couples the rapid voltage rise to the gate node. The rising voltage turns on the ESD switch, shunting the ESD pulse to the other supply. A resistor and a p-channel MOS transistor in series then discharge the gate node to the other supply. The capacitor, resistor, and p-channel transistor form an RC network.

Abstract: A voltage translator uses an n-channel translator transistor to translate an input voltage at its drain to an output voltage at its source. The gate and substrate of the translator transistor are each biased by charge pumps. A reference transistor is also biased by the charge pumps. A reference input voltage is translated to a reference output voltage by the reference transistor. The reference output voltage is compared to a target output voltage by comparators. When the reference output voltage is below the target, the gate charge pump is turned on, raising the gate voltage to both the reference and translator transistors. The higher gate voltage VGATE raises the output voltage VOUT since VOUT=VGATE-VT for a transistor in saturation. When the reference output voltage is above the target, the substrate charge pump is turned on, pulling the substrate bias voltage below ground. The body effect causes the transistor threshold VT to increase as the substrate is pumped.

Abstract: A bus switch has control of the timing of turning on and off the main p-channel and n-channel transistors that connect two network nodes. A pair of cross-coupled NAND gates form a set-reset S-R latch that controls the gates of the main p-channel and n-channel transistors. The S-R latch controls the timing so that the main p-channel and n-channel transistors switch at about the same time, canceling much of each other's injected charge. Since the main p-channel is larger due to the lower hole mobility, an excess of injected charge from the p-channel transistor remains. This excess charge is cancelled by opposite charge injected by compensating transistors. The compensating transistors are also p-channel devices, but are driven with a logical inverse of the gate of the main p-channel transistor. This produces a charge with opposite polarity to the excess charge from the main p-channel transistor.

Abstract: A bus switch has an n-channel bus-switch transistor that connects an input-bus signal to an output bus. A gate protection circuit prevents undershoots on the inputs from coupling to the output when the bus switch isolates the buses. The gate of the bus-switch transistor is driven to ground during isolation mode. When a high-to-low transition of the input-bus signal is detected, a pulse generator generates a pulse. The pulse disconnects the gate from ground. A connecting n-channel transistor with its gate connected to ground connects the gate to the input-bus signal when the undershoot pulls the input-bus signal below ground. Internal circuitry is isolated from the below-ground gate by an isolating n-channel transistor that has its gate driven by the input-bus signal during the pulse. A substrate bias generator is used for N-well processes, but P-well processes use a well protection circuit. The P-well under the bus-switch transistor is disconnected from ground during the generated pulse.

Abstract: A pseudo-emitter-coupled-logic (PECL) receiver has a wide common-mode range. Two current-mirror CMOS differential amplifiers are used. One amplifier has n-channel differential transistors and a p-channel current mirror, while the second amplifier has p-channel differential transistors and an n-channel current mirror. When the input voltages approach power or ground, one type of differential transistor continues to operate even when the other type shuts off. The outputs of the two amplifiers are connected together and each amplifier receives the same differential input signals. The tail-current transistor is self-biased using the current-mirror's gate-bias. This self biasing of each amplifier eliminates the need for an additional voltage reference and allows each amplifier to adjust its biasing over a wide input-voltage range. Thus the common-mode input range is extended using self biasing and complementary amplifiers.

Abstract: A bus switch uses both n-channel and p-channel transistors in parallel to connect two busses. The bus switch can be used on a network card to be plugged into a running network. During hot or live insertion of the network card into a live or hot bus, the network card and a bus switch are in a powered down state. Although n-channel transistors are normally off when the power is off, p-channel transistors can conduct. The hot bus could be disturbed when the bus switch is first connected since the p-channel transistor conducts when its gate is powered down to zero volts. A p-n junction from the p-channel transistor's drain to its substrate can become forward biased, drawing current from the hot bus. These problems are avoided by an isolation circuit that operates without power from a power supply. Instead, a high voltage from the hot bus is routed to the gate of the p-channel transistor, keeping the p-channel transistor turned off during hot insertion.

Abstract: A CMOS output buffer has as pull-downs a smaller driver transistor and a larger driver transistor. Both transistors drive the output low in parallel initially during a voltage transition, but the larger transistor is disabled for the remainder of the output voltage swing when reflections and ringing occur. A pulse is generated by a transition detector when an input to the output buffer transitions low. The pulse generated disables the larger driver for a short period of time but later re-enables the driver. Thus the large driver remains on after the switching is complete, providing large IOH and IOL static currents. The pulse is long enough to keep the large driver disabled while reflections are received and ringing occurs after the voltage transition. A Resistor in series with the smaller driver transistor absorbs these reflections.

Abstract: A pseudo-emitter-coupled-logic (PECL) receiver has a wide common-mode range. Two current-mirror CMOS differential amplifiers are used. One amplifier has n-channel differential transistors and a p-channel current mirror, while the second amplifier has p-channel differential transistors and an n-channel current mirror. When the input voltages approach power or ground, one type of differential transistor continues to operate even when the other type shuts off. The outputs of the two amplifiers are connected together and each amplifier receives the same differential input signals. The tail-current transistor is self-biased using the current-mirror's gate-bias. This self biasing of each amplifier eliminates the need for an additional voltage reference and allows each amplifier to adjust its biasing over a wide input-voltage range. Thus the common-mode input range is extended using self biasing and complementary amplifiers.

Abstract: An n-channel bus switch has a transistor gate boosted above the power supply (Vcc) to increase current drive and reduce the channel resistance of the bus switch. No pulse generator is needed. The gate terminal is connected to a boosted node. When the bus switch is turned on, a pullup transistor drives the boosted node from ground to Vcc. The pulse generator is eliminated by using a Schmidt-trigger to sense the voltage of the boosted node. Once the Schmidt-trigger senses that the voltage of the boosted node is near Vcc, the pull-up is turned off. A delay line first drives the gate of the pullup transistor to a threshold below Vcc using an n-channel pullup, and then drives the gate to Vpp using a p-channel pullup. A delay line then drives the back-side of a capacitor from ground to Vcc. This voltage swing is coupled through the capacitor to the boosted node, driving the boosted node about 1.3 volts above Vcc. A small keeper transistor supplies a small current to the boosted node to counteract any leakage.

Abstract: A twisted-pair current driver is implemented in CMOS. EMI from sharp changes in the current driven is reduced by gradually changing the current driven when the inputs change. The current driver is divided into N differential drivers, each driving one-Nth of the total switching current to the twisted pair. Delay lines delay when input changes are sent to each of the four differential drivers, staggering their response. Either binary or multi-level-transition (MLT-3) data can be transmitted. A binary-to-MLT converter uses a dummy flip-flop to match delays and eliminate encoding glitches. Either the binary or the MLT-3 encoded data is coupled to the inputs of the delay lines and the differential drivers. The mid-level for MLT-3 is driven when both the inputs are high, causing the differential drivers to split the current among the two differential outputs to the twisted pair.

Abstract: A differential-output current driver is constructed entirely of CMOS transistors. Pseudo-ECL levels are reached when a standard resistive termination is connected to the outputs. The current driver can also drive a non-standard termination to the PECL levels. The non-standard termination is low power because it does not draw standby current from power to ground. Current from the current sources within the current driver are assigned to either the switching current or the constant current. The constant current is applied directly to the outputs to drive the termination to a bias point. The switching current is applied to a differential pair of transistors which switch the switching current to one or the other of the differential outputs in response to a differential input. The constant current is combined with any switching current output from the differential transistors and applied to the differential outputs to drive the external termination.

Abstract: A bus switch is constructed from an n-channel transistor. The gate terminal of the n-channel transistor is boosted above the power supply (Vcc) to increase current drive and reduce the channel resistance of the bus switch. The gate terminal is connected to a boosted node. When the bus switch is turned on, a pulse is generated to drive the boosted node from ground to Vcc. The boosted node is also an input of a delay line. After a delay through the delay line, the pulsed pull-up is turned off. Feeding the boosted node to the delay line allows the pulse to be self-timed. The delay line then drives the back-side of a capacitor from ground to Vcc. This voltage swing is coupled through the capacitor to the boosted node, driving the boosted node about 1.3 volts above Vcc. A small keeper transistor supplies a small current to the boosted node to counteract any leakage. This leaker transistor is connected to a charge pump, and the delay line that enables this keeper transistor is also connected to the charge pump.