Abstract: A mixed-signal CMOS integrated semiconductor device exhibits reduced substrate noise coupling between digital and analog circuit functions using selectively formed isolated, high-impurity buried regions between substrate and epitaxial layers. The impedance within the high-impurity regions is relatively lower than the impedance between high-impurity regions, thereby reducing noise-induced potentials, and latchup, within high-impurity regions and noise-induced currents between high-impurity regions. An attenuation network is effectively formed in the semiconductor device layers to reduce noise coupling, the impedance within the high-impurity region acting as the pi attenuation network shunt path. High-impurity regions are formed by selectively diffusing or implanting impurities into bulk lightly-doped, silicon substrate layer prior to growing an epitaxial layer. The high-impurity regions, substrate and epitaxial layers are all of the same conductivity type.

Abstract: A high-speed parallel-data communication approach overcomes skewing problems by transferring digital data with automatic realignment. In one example embodiment, a parallel bus has parallel bus lines adapted to transfer digital data from a data file, along with a synchronizing clock signal. To calibrate the synchronization, the sending module transfers synchronization codes which are sampled and validated according to an edge of the clock signal by a receiving module and then used to time-adjust the edge of the clock signal relative to the synchronization codes. The synchronization codes are implemented to toggle the bus lines with each of the synchronization codes transferred.

Abstract: A hardware-configurable digital filter is adaptable for providing multiple filtering modes. In one embodiment, the digital filter includes a register-based array of logic circuitry, computational circuitry and mode selection circuitry. By reconfiguring data flow within the logic circuitry and the computational circuitry, the mode selection circuitry switches the digital filter between different ones of the multiple filtering modes. Each of the multiplication and addition logic circuits has outputs and inputs selectably coupled to the other of the multiplication and addition logic circuits along a Y direction, with the selectivity being responsive to the mode selection circuitry for arranging the registers as being functionally linear or functionally nonlinear.

Abstract: The present invention embodiment comprises an arrangement of integrated circuits with a UART device that is configurable to operate in a power-reduced mode while the clock frequency of serial data communication remains constant. In one example embodiment, an arrangement of a plurality of integrated circuit devices includes a first integrated circuit device driven by a first clock signal at a first clock rate. The arrangement contains a parallel data bus coupled to communicate with the first integrated circuit device in response to the first clock signal. The arrangement also includes a universal asynchronous receiver/transmitter (UART) chip with a serial communication circuit adapted to communicate serial data at a second rate defined by a second clock signal. The UART chip also encompasses a parallel bus interface circuit responsive to the first clock signal and adapted to pass data between the parallel data bus and the serial communication circuit.

Abstract: A circuit arrangement improves CPU efficiency by processing data through a FIFO circuit of a UART chip using a CPU adapted to detect, and respond with various options to, the current storage capacity of the FIFO circuit. In one example embodiment, a circuit arrangement includes a universal asynchronous receiver/transmitter (UART) chip having a FIFO circuit and an arithmetic logic unit (ALU) adapted to generate an N-bit variable binary signal, wherein the binary signal varies as a function of a current storage capacity of the FIFO circuit. The circuit arrangement further includes a control circuit communicatively coupled with the UART chip that is adapted to read the N-bit variable binary signal and, in response, to control the data flow through the FIFO circuit.

Abstract: An integrated circuit arrangement is reconfigurable in the field to operate in one of a plurality of modes, including a test mode, in response to mode-selecting codes presented via a temporary register in the circuit. In one example embodiment, an arrangement of integrated circuits includes a reconfigurable integrated circuit configured and arranged to operate in one of a plurality of modes. The reconfigurable integrated circuit includes a register adapted to store data for temporary use, with each operating mode of the reconfigurable circuit being selectable in response to mode-selecting data code. An interface circuit is electrically connected to the reconfigurable integrated circuit and is adapted to present the mode-selecting data code to the reconfigurable integrated circuit. A selection circuit is adapted to enable the interface circuit to pass mode-selecting data to the reconfigurable integrated circuit.

Abstract: A configurable universal asynchronous receiver/transmitter (UART) facilitates efforts to upgrade UART functionality in the field and replace older UART devices. In one example embodiment, an integrated circuit includes a universal asynchronous receiver/transmitter configured and arranged to operate in one of a plurality of modes, with each mode being selectable in response to mode-selecting data. The integrated circuit device includes an interface circuit electrically connected to the universal asynchronous receiver/transmitter and adapted to present the mode-selecting data to the universal asynchronous receiver/transmitter. The integrated circuit device also includes a selection circuit adapted to enable the mode-selecting data to pass from the interface circuit to the universal asynchronous receiver/transmitter.

Abstract: The operability and scaleability of electronic circuits is improved using a circuit arrangement that is modular, scaleable, straightforward to implement and allows for simple and safe physical design implementation. According to one example embodiment of the present invention, a reset method and system are used to effect a reset at several peripheral devices that may employ similar and/or different reset strategies. A reset signal generator is coupled to a clock module having an external clock reference and to each of the peripheral devices. A reset clock signal having the reference clock frequency is sent to each of the peripheral devices via clock outputs at the clock module. A synchronization module at each of the peripheral devices is adapted to synchronize the reset signal among all peripheral devices using the clock signal. The clock module holds the reset clock signal for a selected amount of time, and then releases the signal from the external clock.

Abstract: The reliability and operability of semiconductor devices is improved using a circuit arrangement and method that improves the ability to manage data storage and retrieval. According to one example embodiment of the present invention, a memory device includes a dynamically configurable page table having a plurality of pages. The page table is dynamically configurable to at least two organizations, and each page includes a multitude of memory storage locations adapted to store data. A controller is adapted to track memory requests and to configure the page table to one of the at least two organizations during a memory refresh cycle, wherein the configuration is effected in response to the tracked memory requests. In this manner, the page table can be adapted to improve the effectiveness and speed of data storage and retrieval.

Abstract: A pulse-width modulation technique uses a counter load value that alternates between a duty-cycle defining value and its complement. In one embodiment, a pulse-width modulated signal is produced as a function of a control signal used to reload the counter in response to the counter reaching an overflow threshold value. This approach includes storing the counter load value and counting relative to a logic circuit output value which corresponds to either the load value or its complement. The counting is reinitiated using the logic circuit output in response to the counter reaching an overflow threshold value. A specific example application of the above type of PWM approach is directed to implementation in otherwise conventional up/down digital counters such as exists in 80C51-type microcontrollers.

Abstract: An approach for impedance matching a transmission line includes using the actual line impedance. According to one example embodiment, the impedance of a line connecting first and second nodes is calibrated by first driving the line to a steady-state voltage using a first current having a magnitude greater than zero, driving the current to a zero magnitude from the first node and therein inducing a voltage transient. The resultant voltage level on the line at the first node is then measured and analyzed relative to a reference voltage. The result of the comparison is then used to adjust the conductance at the second node.

Abstract: For use with sub-micron CMOS technologies, a gate etch process improves control of the etch profile. Gate stacks utilize N-type or P-type doped amorphous or poly silicon to enhance device performance. However, the different etching characteristics of the N-type versus the P-type amorphous or poly silicon material can result in a localized breakthrough of the underlying thin gate oxide adjacent to the edge of the gate stack, especially in the N doped active regions. According to one example embodiment, this localized breakthrough (“microtrenching”) is avoided by building the gate stacks with undoped amorphous or poly silicon to the desired configuration, masking the gate stacks with a dielectric layer, planarizing the dielectric layer and then implanting the N-type or P-type species into the selected gate stack.

Abstract: The performance of the main regulatory transistor of an on-chip voltage regulator circuit is enhanced when the main transistor is appropriately biased during start up. In an example embodiment, a voltage regulator circuit includes a thin gate oxide transistor as the main regulatory transistor and an operational amplifier that is referenced to a midlevel operating voltage. During start-up, the potential voltage difference is large enough to necessitate the disconnection of the main transistor from the operational amplifier. A voltage divider ladder circuit is used to maintain the gate voltage of the main transistor at the midlevel voltage while a smaller thick gate oxide transistor is used to maintain loop stability and to withstand voltage transients.

Abstract: Useful to inhibit reverse engineering, semiconductor devices and methods therefor include formation of two active regions over a substrate region in the semiconductor device. According to an example embodiment, a dopable link, or region, between two heavily doped regions can be doped to achieve a first polarity type, with the two heavily doped regions of the opposite polarity. If dictated by design requirements, the dopable region is adapted to conductively link the two heavily doped regions. A dielectric is formed over the dopable region and extends over a portion of each of the two heavily doped regions to inhibit silicide formation over edges of the dopable region. In connection with a salicide process, a silicide is then formed adjacent the dielectric and formed over another portion of the two heavily doped regions.

Abstract: In the manufacture of a semiconductor device, a method for forming a layer on a semiconductor substrate compensates for variations in wafer substrate reflectivity. The method includes providing substrate illumination and then adjusting the illumination on the substrate. The method also includes controlling the dispensation of material over the substrate as a function of the adjusted illumination. By compensating for variations in wafer substrate reflectivity, manufacturing processes can realize more consistent photoresist coatings on wafer substrates from one wafer lot to another.

Abstract: A circuit arrangement and method interface multiple functional blocks within an integrated circuit device via a concurrent serial interconnect capable of routing separate serial command, data and clock signals between functional blocks in the device. The concurrent serial interconnect utilizes a plurality of serial ports that are selectively coupled to one another by an interface controller to define one or more logical communication channels between two or more of the serial ports. Each serial port is coupled via a point-to-point interconnection with a port interface in a functional block. In addition, the concurrent serial interconnect facilitates the design of an integrated circuit device by supporting the addition of a serial interconnect to an assemblage of functional blocks, with each functional block associated with one of a plurality of serial ports in the serial interconnect.

Abstract: An arrangement controls an IC designed with multiple “TLM'ed core” circuits, such as multiple CPUs, with each core circuit including its own TAP controller and with multiple TAP controllers enabled a time. For applications typically requiring that control be transferred between such TAP controllers of various core circuits, one embodiment of the present invention expands a multiple “TLM'ed core” circuit design without changing the IEEE JTAG specification and without requiring more scan chains per TAP'ed core. One particular example embodiment includes each of the design's multiple cores including multiple test-access port (TAP) controllers, and including an internal TLM having a TLM register adapted to store a decodable instruction and a supplemental storage circuit adapted to store a coded signal.

Abstract: A semiconductor device is manufactured using an acid treatment process to eliminate the adverse effects of contamination, such as amine-airborne contamination. Consistent with one embodiment of the present invention, the semiconductor device is formed by applying a DUV-type photoresist over the wafer surface, exposing the photoresist to DUV light, treating the exposed photoresist with an acid vapor, and thereafter baking the exposed wafer.

Abstract: According to an example embodiment, the present invention comprises a CMP pad conditioner arrangement. An inlet is configured and arranged for receiving treatment elements. A distribution surface is coupled to the inlet and is configured and arranged to disperse the treatment elements. A multitude of outlets are coupled to the distribution surface and are configured and arranged to dispense the treatment elements onto a CMP pad. Benefits of using this embodiment include enhanced pad cleaning, better slurry dispense, improved wafer quality, and faster production.

Abstract: A circuit arrangement utilizes a common bus for functional operations of logic circuits and for scan testing the logic circuits. In one embodiment, input/output ports and scan test ports of the logic circuits are switchably coupled to a bus. For functionally testing the logic circuits, a predetermined command transmitted over the bus causes the scan test ports to be coupled to the bus and the input/output ports to be decoupled from the bus. Test data may then be transmitted to and from the logic circuits via the bus. When testing is complete, a second predetermined command transmitted over the bus causes the scan test ports to be decoupled from the bus and the input/output ports to be coupled to the bus.