Abstract: A method for making a multi-layered integrated circuit structure, includes depositing a methyl compound spin on glass layer over a substrate. The spin on glass layer is treated by plasma-deposition to form a SiO2 skin on the methyl compound spin on glass layer and then treated again by plasma-deposition to form a cap layer which adheres to the SiO2 skin.

Abstract: A semiconductor fabrication process permits for narrowing linewidths using Optical End of Line Metrology (OELM). OELM involves measuring relative line shortening effects that are inherent in many semiconductor fabrication processes using optical overlay instruments. According to one embodiment, the process involves a frame that has two adjacent sides which are constructed of lines and spaces. The frame is imaged onto a wafer, but the optical line measurements used to implement the frame over-predict actual shortening of the lines.

Abstract: Metal bond pads are formed over active circuitry in a semiconductor chip in a reliable and cost effective manner. According to an example embodiment of the present invention, a metal bond pad is formed over circuitry in the semiconductor chip. A metal layer is formed over the circuitry and the metal bond pad, and a diffusion barrier layer is formed between the metal layer and the metal bond pad. In this manner, additional metal can be formed on the pad site using only one additional mask step, and thicker metal at the pad site improves the reliability of the chip by providing for a metal cushion at the pad useful in subsequent wire bonding processes.

Abstract: In one example embodiment, a method of forming a pattern in a photoresist material includes illuminating a portion of the photoresist material according to the pattern and positioning a filter in a path of the light. The filter includes a number of regions upon which a filtering material has been. The filtering material has a variable characteristic that is independently adjustable for each region to enhance the uniformity of the intensity of the light. Such characteristics include the thickness of the filtering material, the size of the portion of the region that is covered by the filtering material, or a voltage, current, electric field, or magnetic field applied to the filtering material of each region.

Abstract: Chemical Mechanical Processing (CMP) is widely used for manufacturing semiconductors. CMP is very effective for planarizing geometry that are not widely isolated. One limiting aspect of CMP is that the deposition of the layer being planarized generally has an effective distance over which gaps can be filled. These gaps can fill with a residue that adversely effects the resultant semiconductor. A technique that inhibits the accumulation of residue deposits a sacrificial layer of material after deposition of a planarizing layer, but before CMP. This layer is selected so that it fills the gaps from the manufacturing process, but has little abrasive or solvent resistance. CMP is performed after the sacrificial layer is performed. However, since the gaps are filled, residues cannot collect. Then, after the CMP is performed, the sacrificial layer is removed by applying a solvent to the sacrificial layer. The choice of material for the sacrificial layer is also important.

Abstract: An improved gate electrode provides greater tolerances to higher temperature annealing treatments, and is useful in connection with the formation of self-aligned contacts as are needed for high density embedded DRAM applications. Consistent with one embodiment, a process for manufacturing a polycide transistor gate electrode involves forming a cap dielectric and dielectric spacer, with the electrode exhibiting a reduced diffusion transport of dopants between an underlying doped polysilicon layer and an overlying suicide layer. The reduced transport results from the presence of a thin barrier layer between the doped polysilicon layer and silicide layer, and the gate electrode process forms a thermally-oxidized thin polysilicon side-wall film against the polysilicon layer, the barrier layer, the silicide layer, and the cap dielectric layer. The polysilicon side-wall film is used for blocking substantial oxidation of the barrier film.

Abstract: A microprocessor-based serial bus interface circuit arrangement. The interface circuit arrangement includes a processor, a read-only memory circuit, a random access memory circuit, and a port interface circuit arrangement coupled to a local bus. The processor is configured and arranged to perform selected link layer functions of the IEEE 1394 standard. The read-only memory is configured with instructions for causing the processor to perform the selected link layer functions, and the random access memory is utilized by the link layer software. The port interface circuit arrangement is arranged to couple to the 1394 standard serial bus and transfer data between random access memory and the 1394 bus via the local bus responsive to the processor performing the selected link layer functions.

Abstract: A circuit arrangement on a handset for checking paging information transmitted in a personal handyphone system. The circuit arrangement includes a memory portion for storing the identification numbers of the handset and the cell station from which the handset receives calls, and an interrupt generator for comparing transmitted identification numbers of a called handset and a cell station with the stored identification numbers of the handset and the cell station and for generating an interrupt when the stored identification number of the handset matches the transmitted identification number of the called handset and the stored identification number of the cell station matches the transmitted identification number of the cell station.

Abstract: In modern sub-micron technologies with aggressive design rules, it is not always possible to have complete overlap of conductive lines with underlying vias. A process for manufacturing a semiconductor device having metal interconnects reduces or eliminates the recessing of metal in the vias, particularly when the metal in the vias is aluminum or an aluminum alloy. By manipulating the etch chemistry so that the etch rates of the aluminum alloy, the surrounding barrier metals, and the dielectric are comparable, it is possible to perform the metal over etch without forming voids in the exposed portion of the via. By eliminating the voids, thinning of the vias due to the presence of recesses is minimized, and electrical connections are less susceptible to electromigration. Consequently, device yield and reliability are increased.

Abstract: A method for manufacturing a semiconductor device that includes dual gate oxide layers made of two dielectric layers of varying thickness on a single wafer. In an example embodiment, a semiconductor structure is fabricated by providing a first layer of a dielectric over a semiconductor material and covering the first layer with a protective second dielectric layer adapted to mask the first layer. The first and second layers are then removed over a region of the semiconductor material while the second layer is used to protect the first layer, therein leaving the region of semiconductor material substantially exposed. A third layer of dielectric material is formed over the first and second layers and the adjacent exposed semiconductor material region; a gate material is then formed over the third dielectric layer. Finally, an etching step etches through the gate material and underlying layers to the semiconductor material to form a thick gate region and a thin gate region.

Abstract: An apparatus for forming a pattern in a photoresist material includes a light source to provide light for illuminating a portion of the photoresist material according to the pattern and a filter positioned in a path of the light. The filter includes a number of regions upon which a filtering material has been. The filtering material has a variable characteristic that is independently adjustable for each region to enhance the uniformity of the intensity of the light. Such characteristics include the thickness of the filtering material, the size of the portion of the region that is covered by the filtering material, or a voltage, current, electric field, or magnetic field applied to the filtering material of each region.

Abstract: Metal bond pads are formed over active circuitry in a semiconductor chip in a reliable and cost effective manner. According to an example embodiment of the present invention, a metal bond pad is formed over circuitry in the semiconductor chip. A metal layer is formed over the circuitry and the metal bond pad, and a photoresist mask is patterned over the metal layer. The metal layer is etched and the portion of the metal layer not masked with the photoresist is removed. In this manner, additional metal can be formed on the pad site using only one additional mask step, and the thicker metal at the pad site improves the reliability of the chip by providing for a metal cushion at the pad useful in subsequent wire bonding processes.

Abstract: The present invention comprises the electrode assemblies themselves as well as improved plasma plate. The plasma side of the plate is counter bored in the area of the gas inlet holes to an appropriate depth. On the opposite side of the plate, another set of bores are placed around the outsides of the gas inlet feed throughs. These bores are machined to incorporate a set of metallic sleeves. The counter bore on the plasma side of the ceramic is used as the first step in removing the plasma from the ceramic surface. The metallic sleeves are utilized to prevent the plasma from invading the counter bore and touching the surface and to allow the surface to remain electrically uniform and planar to the substrate being etched. The sleeves create a negative charge close to the surface of the ceramic surface but not exposed to the plasma to create a dark space. The dark space mimics an electrically planar surface for the substrate while keeping the hot plasma from direct contact with the ceramic surface.

Abstract: A point-to-point or ring connectable bus bridge replicates a PCI bus serially over a point-to-point or ring connected network and the Fiber Channel interface enhanced by a method for improving link performance provides the serial connection. Participants can appear as resources or masters on the PCI bus and connections can be made to existing bus controllers and existing bus peripherals without redesign.

Abstract: In modern sub-micron technologies with aggressive design rules, it is not always possible to have complete overlap of conductive lines with underlying vias. A process for manufacturing a semiconductor device having metal interconnects reduces or eliminates the recessing of metal in the vias, particularly when the metal in the vias is aluminum or an aluminum alloy. By manipulating the etch chemistry so that the etch rates of the aluminum alloy, the surrounding barrier metals, and the dielectric are comparable, it is possible to perform the metal over etch without forming voids in the exposed portion of the via. By eliminating the voids, thinning of the vias due to the presence of recesses is minimized, and electrical connections are less susceptible to electromigration. Consequently, device yield and reliability are increased.

Abstract: A method of forming a semiconductor device minimizes oxide recessing in a trench of a semiconductor device. In one embodiment, forming a nitride spacer surrounding the top trench corner oxide in a shallow trench isolation region protects the corner oxide from being etched during processing. Oxide recessing in the trench is undesirable since it results in high electric fields around the sharp top corners of the trenches and Vt roll-off of the transistors. According to one example embodiment, STI regions filled with an HDP oxide and having undergone planarization, are masked. The masking substantially covers the HDP oxide and overlaps at least portions of nitride regions. Unmasked areas of the nitride regions are etched away forming nitride spacers on both sides of the HDP oxide fill.

Abstract: According to an example embodiment, the present invention is directed to a configurable semiconductor device wherein the placement of bond wires and bonding pads are assembled to bond internal configuration pads at the die level. One aspect of the invention is a multiple-configuration semiconductor device that includes a die package for housing a die including functional bonding pads and including target bonding pads that are immediately adjacent to one another and designated to be connected to power or common depending on a desired configuration. A bonding wire circuit includes a first plurality of bonding wires respectively connecting the functional bonding pads to selected lead fingers, and further includes a second plurality of bonding wires connecting each of at least two of the immediately-adjacent target bonding pads to power or common.

Abstract: A reverberation processor and method for generating reverberation in a digital audio processing system. The reverberation processor uses register files programmed with tap page and tap offset addresses to gather the audio data for the reverberation taps. The address of each block transferred is determined by the tap number, which selects an offset register to provide a lower portion of the address, and the page number which selects a page register to provide the upper portion of the address. Control logic provides for enabling of the address and initiation of transfers to and from memory on a bus. Dual port register files are used to receive that data for a digital signal processor (DSP). The DSP computes a reverberation result and fills another dual port register file. The register files signal the control logic to initiate transfers when the input data drops below a threshold or the output data exceeds a threshold.

Abstract: A programmable fuse implements redundancy in semiconductor devices and enables the repair of defective elements. In an example embodiment, a fuse is built in the second-to-the-last metal interconnect layer used in the circuit. An opening to expose the fuse is incorporated into an existing mask of the last metal interconnect layer, typically the pad mask. The passivation layer on top of the bond pads is opened to expose the bonding pads. At the same time, a residual oxide window is defined over the fuse. The residual oxide covering the fuse provides for a reliable and reproducible fuse.

Abstract: A semiconductor manufacturing process is used to develop capacitors in compact areas such as at or near the interconnect level. According to one example embodiment, a substrate having a first and second conductor is separated by a dielectric, once the dielectric is removed a trench is formed, and a first material including silicon nitride is deposited over the substrate so that it covers the trench. A second material, including metal, is then deposited over the first material, covering it and the first and second conductors. CMP is then used to remove the metal over the field and isolate the filled metal from adjacent metals causing the silicon nitride to act as a natural CMP etch-stopper and protecting other areas of the interconnect from damage by the CMP.