Patents Assigned to Phison Electronic Corp.
  • Publication number: 20220137877
    Abstract: A memory control method for a memory storage device is provided according to an exemplary embodiment of the disclosure. The method includes: reading first data from a first physical unit in response to a first read command from a host system; performing a first decoding operation on the first data to obtain decoded data corresponding to the first data; storing the decoded data corresponding to the first data in a buffer memory; reading second data from the first physical unit in response to a second read command from the host system; performing a second decoding operation on the second data; and in response to failure of the second decoding operation, searching the buffer memory for the decoded data corresponding to the first data to replace the reading of the second data.
    Type: Application
    Filed: November 26, 2020
    Publication date: May 5, 2022
    Applicant: PHISON ELECTRONICS CORP.
    Inventor: Chia-Hsiung Lai
  • Patent number: 11307982
    Abstract: A data management method, a memory storage device and a memory control circuit unit. The method includes: executing one or more read commands, and recording a physical unit having a first variation of a read count greater than a read disturb threshold as a risk physical unit; and when a data merging process is performed, dividing valid data stored in the risk physical unit into a plurality of copies and copying the copies into a plurality of recycling units.
    Type: Grant
    Filed: September 28, 2020
    Date of Patent: April 19, 2022
    Assignee: PHISON ELECTRONICS CORP.
    Inventors: Kuang-Yao Chang, Shin-Wei Gau
  • Patent number: 11301311
    Abstract: A memory control method for a rewritable non-volatile memory module is provided according to embodiments of the disclosure. The method includes: receiving at least one first read command from a host system; and determining, according to a total data amount of to-be-read data indicated by the at least one first read command, whether to start a pre-read operation. The pre-read operation is configured to pre-read data stored in at least one first logical unit, and the first logical unit is mapped to at least one physical unit.
    Type: Grant
    Filed: October 4, 2019
    Date of Patent: April 12, 2022
    Assignee: PHISON ELECTRONICS CORP.
    Inventor: Chen Yap Tan
  • Publication number: 20220107756
    Abstract: An exemplary embodiment of the invention provides a read voltage control method for a rewritable non-volatile memory module. The method includes: sending a first read command sequence which instructs a reading of a plurality of first memory cells by using a first voltage level to obtain first data; obtaining first adjustment information of a read voltage according to the first data and a channel parameter of the first memory cells, and the channel parameter reflects a channel status of the first memory cells; and adjusting a voltage level of the read voltage from the first voltage level to a second voltage level according to the first adjustment information.
    Type: Application
    Filed: October 27, 2020
    Publication date: April 7, 2022
    Applicant: PHISON ELECTRONICS CORP.
    Inventors: Shih-Jia Zeng, Chun-Wei Tsao, Chih-Wei Wang, Wei Lin
  • Publication number: 20220075714
    Abstract: A data merge method for a rewritable non-volatile memory module including a plurality of physical units is provided. The method includes: selecting at least one first physical unit and at least one second physical unit from the physical units; reading first mapping information from the rewritable non-volatile memory module, and the first mapping information includes mapping information of the first physical unit and mapping information of the second physical unit; copying valid data collected from the first physical unit and valid data collected from the second physical unit to at least one third physical unit of the physical units according to the first mapping information; and when a data volume of valid data copied from the second physical unit to the third physical unit reaches a data volume threshold, stopping collecting valid data from the second physical unit, and continuing collecting valid data from the first physical unit.
    Type: Application
    Filed: September 25, 2020
    Publication date: March 10, 2022
    Applicant: PHISON ELECTRONICS CORP.
    Inventors: Che-Yueh Kuo, Ching-Yu Pan
  • Publication number: 20220075715
    Abstract: A data management method, a memory storage device and a memory control circuit unit. The method includes: executing one or more read commands, and recording a physical unit having a first variation of a read count greater than a read disturb threshold as a risk physical unit; and when a data merging process is performed, dividing valid data stored in the risk physical unit into a plurality of copies and copying the copies into a plurality of recycling units.
    Type: Application
    Filed: September 28, 2020
    Publication date: March 10, 2022
    Applicant: PHISON ELECTRONICS CORP.
    Inventors: Kuang-Yao Chang, Shin-Wei Gau
  • Publication number: 20220051748
    Abstract: An execution method of a firmware code, a memory storage device and a memory control circuit unit are disclosed. The method includes: executing a firmware code in a read only memory; after executing a first part of the firmware code, querying reference information in a reference memory according to index information in the firmware code; and determining, according to the reference information, to continuously execute a second part of the firmware code or switch to execute a replacement program code in the reference memory, so as to complete a startup procedure.
    Type: Application
    Filed: September 26, 2020
    Publication date: February 17, 2022
    Applicant: PHISON ELECTRONICS CORP.
    Inventors: Yi-Feng Li, Chun-Yu Ling
  • Patent number: 11251799
    Abstract: A phase-locked loop circuit calibration method for a memory storage device including a rewritable non-volatile memory module is provided according to an exemplary embodiment of the disclosure. The method includes: receiving a first signal from a host system; generating a jitter signal by the memory storage device; generating a second signal according to the first signal and the jitter signal; performing a phase-lock operation on the second signal to generate a third signal by a phase-locked loop circuit; and calibrating an electrical parameter of the phase-locked loop circuit according to a variation of a time difference between the first signal and the third signal.
    Type: Grant
    Filed: February 17, 2020
    Date of Patent: February 15, 2022
    Assignee: PHISON ELECTRONICS CORP.
    Inventors: Chia-Hui Yu, Wun-Jian Su, Yu-Jung Chiu, Chiao-Chieh Yang
  • Patent number: 11249898
    Abstract: A data merge method for a rewritable non-volatile memory module including a plurality of physical units is provided. The method includes: selecting at least one first physical unit and at least one second physical unit from the physical units; reading first mapping information from the rewritable non-volatile memory module, and the first mapping information includes mapping information of the first physical unit and mapping information of the second physical unit; copying valid data collected from the first physical unit and valid data collected from the second physical unit to at least one third physical unit of the physical units according to the first mapping information; and when a data volume of valid data copied from the second physical unit to the third physical unit reaches a data volume threshold, stopping collecting valid data from the second physical unit, and continuing collecting valid data from the first physical unit.
    Type: Grant
    Filed: September 25, 2020
    Date of Patent: February 15, 2022
    Assignee: PHISON ELECTRONICS CORP.
    Inventors: Che-Yueh Kuo, Ching-Yu Pan
  • Patent number: 11238902
    Abstract: A circuit layout structure and a memory storage device are disclosed. The circuit layout structure includes a plurality of first volatile memory modules, a plurality of second volatile memory modules, a first data line, a second data line, a first clock enable signal line and a second clock enable signal line. The first data line is configured to access the first volatile memory modules in parallel by a first sequential bit group. The second data line is configured to access the second volatile memory modules in parallel by a second sequential bit group. The first clock enable signal line and the second clock enable signal line are configured to control the first volatile memory modules and the second volatile memory modules to enter a self-refresh mode respectively.
    Type: Grant
    Filed: April 27, 2020
    Date of Patent: February 1, 2022
    Assignee: PHISON ELECTRONICS CORP.
    Inventors: Ming-Chien Huang, Chien Ho Liao
  • Publication number: 20220027089
    Abstract: A memory control method, a memory storage device and a memory control circuit unit are provided. The method includes: determining a retry threshold value according to decoding history information which includes information related to at least one first decoding operation previously performed; and determining whether to enter a second decoding mode according to the retry threshold value after at least one second decoding operation performed based on a first decoding mode is failed. A decoding ability of the second decoding mode is higher than a decoding ability of the first decoding mode.
    Type: Application
    Filed: August 17, 2020
    Publication date: January 27, 2022
    Applicant: PHISON ELECTRONICS CORP.
    Inventors: Shih-Jia Zeng, Yu-Siang Yang, Szu-Wei Chen, Wei Lin
  • Patent number: 11221946
    Abstract: A data arrangement method, a memory storage device and a memory control circuit unit are provided. The data arrangement method includes: receiving a command from a host, and the command includes a data range; calculating a data disarranged degree according to a logical estimated value of a plurality of logical block addresses of the data range and a physical estimated value of a plurality of physical erasing units mapped to the plurality of logical block addresses of the data range; and determining whether to perform a data arrangement operation according to the data disarranged degree and a threshold to move data in the plurality of physical erasing units according to the plurality of logical block addresses.
    Type: Grant
    Filed: March 30, 2020
    Date of Patent: January 11, 2022
    Assignee: PHISON ELECTRONICS CORP.
    Inventor: Kok-Yong Tan
  • Patent number: 11216334
    Abstract: A data reading method is provided. The method includes: according to a first read command received from a host system, sending a first read command sequence, which is configured to instruct a reading of a plurality of physical units of the rewritable non-volatile memory module to obtain first data; identifying data stored in at least one first physical unit in the physical units as uncorrectable data according to the first data; according to a second command received from the host system, sending a second read command sequence, which is configured to instruct a reading of the physical units of the rewritable non-volatile memory module to obtain second data; generating response data corresponding to the second read command according to the second data and padding data, which is configured to replace the data read from the at least one first physical unit; and transmitting the response data to the host system.
    Type: Grant
    Filed: August 26, 2020
    Date of Patent: January 4, 2022
    Assignee: PHISON ELECTRONICS CORP.
    Inventors: Wei-Jeng Wang, Shao-Hung Lu
  • Patent number: 11216217
    Abstract: A data transfer method includes: instructing a first memory storage device to disable a data encryption function activated by default; and sending a write command to the first memory storage device under a status that the data encryption function of the first memory storage device is disabled. The write command instructs a storing of encryption information of encrypted data to the first memory storage device. The encryption information is not generated by the first memory storage device and is unreadable by a normal read command.
    Type: Grant
    Filed: April 14, 2020
    Date of Patent: January 4, 2022
    Assignee: PHISON ELECTRONICS CORP.
    Inventor: Chun-Yang Hu
  • Publication number: 20210397347
    Abstract: A data protection method, a memory storage device and a memory control circuit unit are provided. The method includes: setting a plurality of disk array tags corresponding to a plurality of word lines and a plurality of memory planes, and the plurality of disk array tags corresponding to one of the word lines connected to one of the memory planes are at least partially identical to the plurality of disk array tags corresponding to another one of the word lines connected to another one of the memory planes; receiving a write command and data corresponding to the write command from a host system; and sequentially writing the data into the plurality of word lines and the plurality of memory planes corresponding to the plurality of disk array tags.
    Type: Application
    Filed: July 6, 2020
    Publication date: December 23, 2021
    Applicant: PHISON ELECTRONICS CORP.
    Inventors: Wei Lin, Yu-Cheng Hsu, Hsiao-Yi Lin, Yu-Siang Yang
  • Publication number: 20210397375
    Abstract: A memory control method for a rewritable non-volatile memory module is provided according to an exemplary embodiment of the disclosure. The method includes: collecting valid data from a source unit; copying a first logical to physical mapping table corresponding to the source unit to generate a second logical to physical mapping table; updating the second logical to physical mapping table according to a physical address of a recycling unit expected to be written, and the second logical to physical mapping table is recorded with mapping information corresponding to the recycling unit; copying the valid data from the source unit into the recycling unit; and updating first management information according to the second logical to physical mapping table.
    Type: Application
    Filed: August 10, 2020
    Publication date: December 23, 2021
    Applicant: PHISON ELECTRONICS CORP.
    Inventors: Che-Yueh Kuo, Li Hsun Lien
  • Patent number: 11206157
    Abstract: A calibration method of an equalizer circuit for a memory storage device is disclosed. The calibration method includes: receiving a first signal; adjusting, by the equalizer circuit, the first signal according to a control parameter to output a second signal; generating a first sampling signal according to a first reference signal and the second signal, wherein the first sampling signal reflects data transmitted by the first signal; and generating a second sampling signal according to a second reference signal and the second signal and adjusting the control parameter according to the second sampling signal to calibrate the equalizer circuit, wherein a voltage value of the first reference signal is different from a voltage value of the second reference signal.
    Type: Grant
    Filed: October 12, 2020
    Date of Patent: December 21, 2021
    Assignee: PHISON ELECTRONICS CORP.
    Inventors: Zhen-Hong Hung, Sheng-Wen Chen, Shih-Yang Sun
  • Patent number: 11190217
    Abstract: A data writing method, a memory controlling circuit unit and a memory storage device are provided. The method includes: obtaining a data; encoding a plurality of sub-data in the data to obtain a plurality of first error checking and correction codes respectively corresponding to the plurality of sub-data; writing the plurality of sub-data and the plurality of first error checking and correction codes into a first physical programming unit; encoding the plurality of sub-data to obtain a second error checking and correction code; and writing the second error checking and correction code into a second physical programming unit.
    Type: Grant
    Filed: February 12, 2020
    Date of Patent: November 30, 2021
    Assignee: PHISON ELECTRONICS CORP.
    Inventors: Yu-Hsiang Lin, Shao-Wei Yen, Chih-Kang Yeh
  • Publication number: 20210357145
    Abstract: A data writing method for a rewritable non-volatile memory module is provided according to embodiments of the disclosure. The method includes: writing first-type data into a first physical unit at a first write speed; and writing second-type data into a second physical unit at a second write speed. The first-type data is different from the second-type data, and the first write speed is different from the second write speed.
    Type: Application
    Filed: July 3, 2020
    Publication date: November 18, 2021
    Applicant: PHISON ELECTRONICS CORP.
    Inventors: Wei-Cheng Li, Yu-Chung Shen, Wei-Liang Huang, Chao-Kai Zhang
  • Publication number: 20210342097
    Abstract: A data writing method, a memory control circuit unit, and a memory storage apparatus are provided. The method includes: receiving a write command from a host system; and determining whether to write a data corresponding to the write command into a first area or a second area according to a write amplification factor of the first area, where if it is determined to write the data into the second area, copying the written data to the first area after writing the data.
    Type: Application
    Filed: May 22, 2020
    Publication date: November 4, 2021
    Applicant: PHISON ELECTRONICS CORP.
    Inventors: Ping-Chuan Lin, Hsiang-Jui Huang, Ping-Yu Hsieh, Tsung-Ju Wu